Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12218205 | 2D-channel transistor structure with source-drain engineering | Khaderbad Mrunal Abhijith, Tzer-Min Shen | 2025-02-04 |
| 12166079 | 2D channel transistors with low contact resistance | Mrunal A. Khaderbad, Wei-Yen Woon | 2024-12-10 |
| 12087819 | Dual channel structure | Mrunal A. Khaderbad, Keng-Chu Lin, Tzer-Min Shen | 2024-09-10 |
| 12068374 | Method of dopant deactivation underneath gate | Kai-Chieh Yang, Ken-Ichi Goto, Wei-Hao Wu, Yuan-Chen Sun, Zhiqiang Wu | 2024-08-20 |
| 11798985 | Methods for manufacturing isolation layers in stacked transistor structures | Mrunal A. Khaderbad, Huicheng Chang, Ko-Feng Chen, Keng-Chu Lin | 2023-10-24 |
| 11728391 | 2d-channel transistor structure with source-drain engineering | Khaderbad Mrunal Abhijith, Tzer-Min Shen | 2023-08-15 |
| 11476333 | Dual channel structure | Mrunal A. Khaderbad, Keng-Chu Lin, Tzer-Min Shen | 2022-10-18 |
| 11450666 | Semiconductor devices including two-dimensional material and methods of fabrication thereof | Mrunal A. Khaderbad | 2022-09-20 |
| 10985246 | MOSFET with selective dopant deactivation underneath gate | Kai-Chieh Yang, Wei-Hao Wu, Ken-Ichi Goto, Zhiqiang Wu, Yuan-Chen Sun | 2021-04-20 |
| 10157985 | MOSFET with selective dopant deactivation underneath gate | Kai-Chieh Yang, Wei-Hao Wu, Ken-Ichi Goto, Zhiqiang Wu, Yuan-Chen Sun | 2018-12-18 |
| 9263345 | SOI transistors with improved source/drain structures with enhanced strain | Ken-Ichi Goto, Ching-Chang Wu, Tzer-Min Shen | 2016-02-16 |
| 9153662 | MOSFET with selective dopant deactivation underneath gate | Kai-Chieh Yang, Wei-Hao Wu, Ken-Ichi Goto, Zhiqiang Wu, Yuan-Chen Sun | 2015-10-06 |
| 8993424 | Method for forming a semiconductor transistor device with optimized dopant profile | Chia-Wen Liu, Tsung-Hsing Yu, Wei-Hao Wu, Ken-Ichi Goto, Tzer-Min Shen +1 more | 2015-03-31 |