Issued Patents All Time
Showing 1–25 of 263 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12426325 | Semiconductor device structure with nanostructure | Sai-Hooi Yeong, Bo-Feng Young | 2025-09-23 |
| 12414357 | Self-aligned metal gate for multigate device | Guan-Lin Chen, Chih-Hao Wang, Shi Ning Ju, Jui-Chien Huang, Kuo-Cheng Chiang +1 more | 2025-09-09 |
| 12408440 | Method of making amphi-FET structure and method of designing | Chih-Yu Lai, Chih-Liang Chen, Chi-Yu Lu, Shang-Syuan Ciou, Hui-Zhong Zhuang +1 more | 2025-09-02 |
| 12402376 | High-voltage nano-sheet transistor | Yu-Xuan Huang, Chia-En Huang, Kuan-Lun Cheng, Yih Wang | 2025-08-26 |
| 12389670 | Air spacer and capping structures in semiconductor devices | Lin-Yu Huang, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Kuan-Lun Cheng | 2025-08-12 |
| 12382717 | Semiconductor device and method of forming thereof | Kuo-Cheng Ching, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang | 2025-08-05 |
| 12368078 | Dual-side power rail design and method of making same | Chih-Chao Chou, Yi-Hsun Chiu, Shang-Wen Chang, Chih-Hao Wang | 2025-07-22 |
| 12347690 | Method for metal gate cut and structure thereof | Pei-Yu Wang, Zhi-Chang Lin, Kuan-Lun Cheng | 2025-07-01 |
| 12342613 | Low leakage device | Cheng-Ting Chung, Kuan-Lun Cheng | 2025-06-24 |
| 12300739 | Metal oxide interlayer structure for NFET and PFET | Min Cao, Pei-Yu Wang, Sai-Hooi Yeong, Kuan-Lun Cheng, Chih-Hao Wang | 2025-05-13 |
| 12302640 | Integrated circuit structure and method with hybrid orientation for FinFET | Tzer-Min Shen, Zhiqiang Wu, Chung-Cheng Wu, Kuan-Lun Cheng, Chih-Hao Wang +1 more | 2025-05-13 |
| 12272751 | Negative capacitance transistor with a diffusion blocking layer | Chi-Hsing Hsu, Kuan-Lun Cheng, Chih-Hao Wang, Sai-Hooi Yeong | 2025-04-08 |
| 12266594 | Method of making semiconductor device having self-aligned interconnect structure | Chih-Yu Lai, Chih-Liang Chen, Chi-Yu Lu, Shang-Syuan Ciou, Hui-Zhong Zhuang +1 more | 2025-04-01 |
| 12243780 | Semiconductor device structure and method for forming the same | Yu-Xuan Huang, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao, Jung-Hung Chang +3 more | 2025-03-04 |
| 12237233 | Backside power rail for physical failure analysis (PFA) | Chih-Chao Chou, Yi-Hsun Chiu, Shang-Wen Chang, Chih-Hao Wang | 2025-02-25 |
| 12230572 | Backside signal interconnection | Yu-Xuan Huang, Yi-Hsun Chiu, Yi-Bo Liao, Kuan-Lun Cheng, Wei-Cheng Lin +6 more | 2025-02-18 |
| 12224348 | Semiconductor device structure and method for forming the same | Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang | 2025-02-11 |
| 12218136 | Semiconductor device having a Fin at a S/D region and a semiconductor contact or silicide interfacing therewith | Kuo-Cheng Ching, Kuan-Lun Cheng, Chih-Hao Wang | 2025-02-04 |
| 12218057 | Integrated circuit with backside interconnections and method of making same | Shih-Wei Peng, Te-Hsin Chiu, Wei-An Lai, Jiann-Tyng Tzeng | 2025-02-04 |
| 12211921 | Method for forming FinFET devices with a fin top hardmask | Kuo-Cheng Ching, Kai-Chieh Yang, Kuan-Lun Cheng, Chih-Hao Wang | 2025-01-28 |
| 12205848 | FinFET gate structure and related methods | Cheng-Ting Chung, Kuan-Lun Cheng | 2025-01-21 |
| 12199030 | Semiconductor devices including decoupling capacitors | Yu-Xuan Huang, Hou-Yu Chen, Kuan-Lun Cheng, Chung-Hui Chen | 2025-01-14 |
| 12199095 | Fin field effect transistors having vertically stacked nano-sheet | Wang-Chun Huang, Chih-Hao Wang, Kuan-Lun Cheng | 2025-01-14 |
| 12191307 | Multi-gate device and related methods | Kuo-Cheng Ching, Kuan-Lun Cheng, Chih-Hao Wang | 2025-01-07 |
| 12183736 | Backside PN junction diode | Yu-Xuan Huang, Jam-Wem Lee, Kuo-Ji Chen, Kuan-Lun Cheng | 2024-12-31 |