Issued Patents All Time
Showing 1–25 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12388013 | Three dimensional integrated circuit with monolithic inter-tier vias (MIV) | Shih-Wei Peng, Jiann-Tyng Tzeng, Kam-Tou Sio, Wei-Cheng Lin | 2025-08-12 |
| 12388016 | Deep lines and shallow lines in signal conducting paths | Te-Hsin Chiu, Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng, Chia-Tien Wu | 2025-08-12 |
| 12307183 | Variable width nano-sheet field-effect transistor cell structure | Wei-Cheng Lin, Yan-Hao Chen, Jiann-Tyng Tzeng, Lipen Yuan, Hui-Zhong Zhuang +1 more | 2025-05-20 |
| 12288785 | Layout designs of integrated circuits having backside routing tracks | Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2025-04-29 |
| 12230572 | Backside signal interconnection | Yu-Xuan Huang, Ching-Wei Tsai, Yi-Hsun Chiu, Yi-Bo Liao, Kuan-Lun Cheng +6 more | 2025-02-18 |
| 12218050 | Manufacturing method for semiconductor device | Te-Hsin Chiu, Meng-Hung Shen, Wei-Cheng Lin, Jiann-Tyng Tzeng, Kam-Tou Sio | 2025-02-04 |
| 12218057 | Integrated circuit with backside interconnections and method of making same | Shih-Wei Peng, Te-Hsin Chiu, Ching-Wei Tsai, Jiann-Tyng Tzeng | 2025-02-04 |
| 12218141 | Hybrid fin field-effect transistor cell structures and related methods | Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen | 2025-02-04 |
| 12204838 | Structure and method for tying off dummy gate in semiconductor device | Jiann-Tyng Tzeng, Shih-Wei Peng, Meng-Hung Shen | 2025-01-21 |
| 12101922 | Memory device and layout, manufacturing method of the same | Te-Hsin Chiu, Jiann-Tyng Tzeng, Shih-Wei Peng | 2024-09-24 |
| 12086524 | Semiconductor device having more similar cell densities in alternating rows | Wei-Cheng Lin, Hui-Ting Yang, Jiann-Tyng Tzeng, Lipen Yuan | 2024-09-10 |
| 12068305 | Multiple fin height integrated circuit | Wei-Cheng Lin, Hui-Ting Yang, Jiann-Tyng Tzeng, Lipen Yuan | 2024-08-20 |
| 11990477 | Hybrid fin field-effect transistor cell structures and related methods | Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen | 2024-05-21 |
| 11942469 | Backside conducting lines in integrated circuits | Shih-Wei Peng, Te-Hsin Chiu, Jiann-Tyng Tzeng, Chung-Hsing Wang | 2024-03-26 |
| 11923369 | Integrated circuit, system and method of forming the same | Te-Hsin Chiu, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-03-05 |
| 11923297 | Apparatus and methods for generating a circuit with high density routing layout | Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-03-05 |
| 11916077 | Method for routing local interconnect structure at same level as reference metal line | Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young +5 more | 2024-02-27 |
| 11908852 | Layout designs of integrated circuits having backside routing tracks | Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2024-02-20 |
| 11854786 | Deep lines and shallow lines in signal conducting paths | Te-Hsin Chiu, Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng, Chia-Tien Wu | 2023-12-26 |
| 11797746 | Method of forming semiconductor device having more similar cell densities in alternating rows | Wei-Cheng Lin, Hui-Ting Yang, Jiann-Tyng Tzeng, Lipen Yuan | 2023-10-24 |
| 11769723 | Three dimensional integrated circuit with monolithic inter-tier vias (MIV) | Shih-Wei Peng, Jiann-Tyng Tzeng, Kam-Tou Sio, Wei-Cheng Lin | 2023-09-26 |
| 11756876 | Semiconductor devices having power rails and signal tracks arranged in different layer | Wei-Cheng Lin, Jiann-Tyng Tzeng | 2023-09-12 |
| 11737254 | Memory device and layout, manufacturing method of the same | Te-Hsin Chiu, Jiann-Tyng Tzeng, Shih-Wei Peng | 2023-08-22 |
| 11721576 | Semiconductor devices and methods of manufacturing thereof | Te-Hsin Chiu, Shih-Wei Peng, Jiann-Tyng Tzeng | 2023-08-08 |
| 11658119 | Backside signal interconnection | Yu-Xuan Huang, Ching-Wei Tsai, Yi-Hsun Chiu, Yi-Bo Liao, Kuan-Lun Cheng +6 more | 2023-05-23 |