Issued Patents All Time
Showing 1–25 of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417980 | First metal structure, layout, and method | Chi-Yu Lu, Chih-Liang Chen, Chia-Tien Wu, Shang-Hsuan CHIU | 2025-09-16 |
| 12408440 | Method of making amphi-FET structure and method of designing | Chih-Liang Chen, Chi-Yu Lu, Shang-Syuan Ciou, Hui-Zhong Zhuang, Ching-Wei Tsai +1 more | 2025-09-02 |
| 12364006 | Integrated circuit and method of forming same | Chih-Liang Chen | 2025-07-15 |
| 12346644 | Arrangement of source or drain conductors of transistor | Chih-Liang Chen, Chi-Yu Lu, Shang-Hsuan CHIU | 2025-07-01 |
| 12266594 | Method of making semiconductor device having self-aligned interconnect structure | Chih-Liang Chen, Chi-Yu Lu, Shang-Syuan Ciou, Hui-Zhong Zhuang, Ching-Wei Tsai +1 more | 2025-04-01 |
| 12243822 | Method of manufacturing integrated circuit | Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien | 2025-03-04 |
| 12218058 | Integrated circuits having stacked transistors and backside power nodes | Chih-Liang Chen, Li-Chun Tien | 2025-02-04 |
| 12087801 | Deep trench isolations and methods of forming the same | Cheng-Hsien Chou, Shih Pei Chou, Yen-Ting Chiang, Hsiao-Hui Tseng, Min-Ying Tsai | 2024-09-10 |
| 12080738 | Image sensor having stacked metal oxide films as fixed charge film | Min-Ying Tsai, Yeur-Luen Tu, Hai-Dang Trinh, Cheng-Yuan Tsai | 2024-09-03 |
| 12057390 | Source/drain isolation structure, layout, and method | Chi-Yu Lu, Yi-Hsun Chiu, Chih-Liang Chen, Shang-Hsuan CHIU | 2024-08-06 |
| 12034009 | Semiconductor device segmented interconnect | Chih-Liang Chen, Ching-Wei Tsai, Shang-Wen Chang, Li-Chun Tien | 2024-07-09 |
| 12009362 | Method of making amphi-FET structure and method of designing | Chih-Liang Chen, Chi-Yu Lu, Shang-Syuan Ciou, Hui-Zhong Zhuang, Ching-Wei Tsai +1 more | 2024-06-11 |
| 11862562 | Integrated circuit conductive line arrangement for circuit structures, and method | Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien | 2024-01-02 |
| 11854940 | Semiconductor device having self-aligned interconnect structure and method of making | Chih-Liang Chen, Chi-Yu Lu, Shang-Syuan Ciou, Hui-Zhong Zhuang, Ching-Wei Tsai +1 more | 2023-12-26 |
| 11853670 | Arrangement of source or drain conductors of transistor | Chih-Liang Chen, Chi-Yu Lu, Shang-Hsuan CHIU | 2023-12-26 |
| 11764213 | Amphi-FET structure, method of making and method of designing | Chih-Liang Chen, Chi-Yu Lu, Shang-Syuan Ciou, Hui-Zhong Zhuang, Ching-Wei Tsai +1 more | 2023-09-19 |
| 11217621 | Deep trench isolations and methods of forming the same | Cheng-Hsien Chou, Shih Pei Chou, Yen-Ting Chiang, Hsiao-Hui Tseng, Min-Ying Tsai | 2022-01-04 |
| 11101307 | Image sensor having stacked conformal films | Min-Ying Tsai, Yeur-Luen Tu, Hai-Dang Trinh, Cheng-Yuan Tsai | 2021-08-24 |
| 10964746 | Deep trench isolation shrinkage method for enhanced device performance | Cheng-Hsien Chou, Shih Pei Chou, Sheng-Chau Chen, Chih-Ta Chen, Yeur-Luen Tu +1 more | 2021-03-30 |
| 10868058 | Photodiode gate dielectric protection layer | Cheng-Hsien Chou, Wen-I Hsu, Tsun-Kai Tsao, Jiech-Fun Lu, Yeur-Luen Tu | 2020-12-15 |
| 10868050 | Backside illuminated image sensor with negatively charged layer | Shyh-Fann Ting, Cheng-Ta Wu, Yeur-Luen Tu, Ching-Chun Wang | 2020-12-15 |
| 10325956 | Deep trench isolation shrinkage method for enhanced device performance | Cheng-Hsien Chou, Shih Pei Chou, Sheng-Chau Chen, Chih-Ta Chen, Yeur-Luen Tu +1 more | 2019-06-18 |
| 10170539 | Stacked capacitor with enhanced capacitance | Szu-Yu Wang, Yeur-Luen Tu | 2019-01-01 |
| 10163949 | Image device having multi-layered refractive layer on back surface | Min-Ying Tsai, Yeur-Luen Tu, Hai-Dang Trinh, Cheng-Yuan Tsai | 2018-12-25 |
| 10163947 | Photodiode gate dielectric protection layer | Cheng-Hsien Chou, Wen-I Hsu, Tsun-Kai Tsao, Jiech-Fun Lu, Yeur-Luen Tu | 2018-12-25 |