Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11955554 | Method of fabricating a multi-gate device | Hung-Li Chiang, Chia-Wen Liu, Yi-Ming Sheu, Zhiqiang Wu, Chung-Cheng Wu +1 more | 2024-04-09 |
| 11942134 | Memory circuit and write method | Tzer-Min Shen, Zhiqiang Wu | 2024-03-26 |
| 11508427 | Memory circuit and write method | Tzer-Min Shen, Zhiqiang Wu | 2022-11-22 |
| 11393926 | Multi-gate device | Hung-Li Chiang, Chia-Wen Liu, Yi-Ming Sheu, Zhiqiang Wu, Chung-Cheng Wu +1 more | 2022-07-19 |
| 11158542 | Semiconductor device structure with semiconductor wire | Hung-Li Chiang, I-Sheng Chen, Tzu-Chiang Chen, Tung Ying Lee, Szu-Wei Huang | 2021-10-26 |
| 11145762 | Multi-gate device | Hung-Li Chiang, Chia-Wen Liu, Yi-Ming Sheu, Zhiqiang Wu, Chung-Cheng Wu +1 more | 2021-10-12 |
| 11043423 | Threshold voltage adjustment for a gate-all-around semiconductor structure | Hung-Li Chiang, Szu-Wei Huang, Jon-Hsu Ho, Chih Chieh Yeh, Wen-Hsing Hsieh +2 more | 2021-06-22 |
| 10879130 | Semiconductor device structure with semiconductor wire | Hung-Li Chiang, I-Sheng Chen, Tzu-Chiang Chen, Tung Ying Lee, Szu-Wei Huang | 2020-12-29 |
| 10438851 | Threshold voltage adjustment for a gate-all-around semiconductor structure | Hung-Li Chiang, Szu-Wei Huang, Jon-Hsu Ho, Chih Chieh Yeh, Wen-Hsing Hsieh +2 more | 2019-10-08 |
| 10290546 | Threshold voltage adjustment for a gate-all-around semiconductor structure | Hung-Li Chiang, Szu-Wei Huang, Jon-Hsu Ho, Chih Chieh Yeh, Wen-Hsing Hsieh +2 more | 2019-05-14 |
| 10290548 | Semiconductor device structure with semiconductor wire | Hung-Li Chiang, I-Sheng Chen, Tzu-Chiang Chen, Tung Ying Lee, Szu-Wei Huang | 2019-05-14 |
| 10008603 | Multi-gate device and method of fabrication thereof | Hung-Li Chiang, Chia-Wen Liu, Yi-Ming Sheu, Zhiqiang Wu, Chung-Cheng Wu +1 more | 2018-06-26 |