Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12396240 | Source/drain silicide for multigate device performance and method of fabricating thereof | Chih-Ching Wang, Chung-I Yang, Wen-Hsing Hsieh, Chung-Wei Wu, Zhiqiang Wu | 2025-08-19 |
| 12361199 | Integrated circuit layout generation method | Ke-Ying Su, Ke-Wei Su, Liang Chen, Wen-Hsing Hsieh, Wen-Koi Lai +4 more | 2025-07-15 |
| 12317526 | Multi-gate devices and fabricating the same with etch rate modulation | Chih-Ching Wang, Chung-I Yang, Wen-Hsing Hsieh, Kuan-Lun Cheng, Chung-Wei Wu +1 more | 2025-05-27 |
| 12300754 | Channel configurations with stacked segments for gate-all-around based devices and methods of fabrication thereof | Chih-Ching Wang, Wen-Hsing Hsieh, Kuan-Lun Cheng, Zhiqiang Wu | 2025-05-13 |
| 12218214 | Source/drain silicide for multigate device performance and method of fabricating thereof | Chih-Ching Wang, Chung-I Yang, Wen-Hsing Hsieh, Chung-Wei Wu, Zhiqiang Wu | 2025-02-04 |
| 12125848 | Semiconductor device structure incorporating air gap | Chih-Ching Wang, Chun Chung Su, Chung-Wei Wu, Kuan-Lun Cheng, Wen-Hsing Hsieh +2 more | 2024-10-22 |
| 12040381 | Method of manufacturing semiconductor devices and semiconductor devices | Cheng-Yi Peng, Wen-Yuan Chen, Wen-Hsing Hsieh, Yi-Ju Hsu, Song-Bor Lee +1 more | 2024-07-16 |
| 11949001 | Multi-gate devices and fabricating the same with etch rate modulation | Chih-Ching Wang, Chung-I Yang, Wen-Hsing Hsieh, Kuan-Lun Cheng, Chung-Wei Wu +1 more | 2024-04-02 |
| 11908919 | Multi-gate devices with multi-layer inner spacers and fabrication methods thereof | Chih-Ching Wang, Wen-Hsing Hsieh, Kuan-Lun Cheng, Chung-Wei Wu, Zhiqiang Wu | 2024-02-20 |
| 11907636 | Integrated circuit layout generation method | Ke-Ying Su, Ke-Wei Su, Liang Chen, Wen-Hsing Hsieh, Wen-Koi Lai +4 more | 2024-02-20 |
| 11626400 | Semiconductor device structure incorporating air gap | Chih-Ching Wang, Wen-Yuan Chen, Chun Chung Su, Wen-Hsing Hsieh, Kuan-Lun Cheng +2 more | 2023-04-11 |
| 11621343 | Method of manufacturing semiconductor devices and semiconductor devices | Cheng-Yi Peng, Wen-Yuan Chen, Wen-Hsing Hsieh, Yi-Ju Hsu, Song-Bor Lee +1 more | 2023-04-04 |
| 11616151 | Channel configuration for improving multigate device performance and method of fabrication thereof | Chih-Ching Wang, Wen-Hsing Hsieh, Kuan-Lun Cheng, Zhiqiang Wu | 2023-03-28 |
| 11508807 | Semiconductor device having nanosheet transistor and methods of fabrication thereof | Chih-Ching Wang, Wen-Hsing Hsieh, Wen-Yuan Chen, Chia-Ying Su, Chung-Wei Wu +1 more | 2022-11-22 |
| 11392749 | Integrated circuit layout generation method and system | Ke-Ying Su, Ke-Wei Su, Liang Chen, Wen-Hsing Hsieh, Wen-Koi Lai +4 more | 2022-07-19 |
| 11282943 | Multi-gate devices and fabricating the same with etch rate modulation | Chih-Ching Wang, Chung-I Yang, Wen-Hsing Hsieh, Kuan-Lun Cheng, Chung-Wei Wu +1 more | 2022-03-22 |
| 11101360 | Method of manufacturing a semiconductor device and a semiconductor device | Cheng-Yi Peng, Wen-Hsing Hsieh, Wen-Yuan Chen, Song-Bor Lee, Bor-Zen Tien | 2021-08-24 |
| 11069791 | Method of manufacturing semiconductor devices and semiconductor devices | Cheng-Yi Peng, Wen-Yuan Chen, Wen-Hsing Hsieh, Yi-Ju Hsu, Song-Bor Lee +1 more | 2021-07-20 |
| 11043423 | Threshold voltage adjustment for a gate-all-around semiconductor structure | Hung-Li Chiang, Szu-Wei Huang, Huan-Sheng Wei, Chih Chieh Yeh, Wen-Hsing Hsieh +2 more | 2021-06-22 |
| 10846456 | Integrated circuit modeling methods and systems | Ke-Ying Su, Ke-Wei Su, Liang Chen, Wen-Hsing Hsieh, Wen-Koi Lai +4 more | 2020-11-24 |
| 10438851 | Threshold voltage adjustment for a gate-all-around semiconductor structure | Hung-Li Chiang, Szu-Wei Huang, Huan-Sheng Wei, Chih Chieh Yeh, Wen-Hsing Hsieh +2 more | 2019-10-08 |
| 10367063 | Semiconductor device including a semiconductor sheet interconnecting a source region and a drain region | Hao Tang, Shao-Hwang Sia, Wen-Hsing Hsieh, Ching-Wei Tsai | 2019-07-30 |
| 10290546 | Threshold voltage adjustment for a gate-all-around semiconductor structure | Hung-Li Chiang, Szu-Wei Huang, Huan-Sheng Wei, Chih Chieh Yeh, Wen-Hsing Hsieh +2 more | 2019-05-14 |
| 9711596 | Semiconductor device including a semiconductor sheet interconnecting a source region and a drain region | Hao Tang, Shao-Hwang Sia, Wen-Hsing Hsieh, Ching-Wei Tsai | 2017-07-18 |
| 9620500 | Series-connected transistor structure | Chin-Chi Wang, Chien-Chih Lee, Tien-Wei Chiang, Ching-Wei Tsai, Chih-Ching Wang +1 more | 2017-04-11 |