Issued Patents All Time
Showing 101–125 of 160 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9653604 | Semiconductor device and manufacturing method thereof | Carlos H. Diaz | 2017-05-16 |
| 9653457 | Stacked device and associated layout structure | Ta-Pen Guo, Carlos H. Diaz, Chih-Hao Wang | 2017-05-16 |
| 9647117 | Apparatus and method for forming semiconductor contacts | — | 2017-05-09 |
| 9640645 | Semiconductor device with silicide | Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz | 2017-05-02 |
| 9634132 | Semiconductor structures and methods for multi-level band gap energy of nanowire transistors to improve drive current | Tsung-Hsing Yu, Chia-Wen Liu, Yeh Hsu | 2017-04-25 |
| 9634091 | Silicon and silicon germanium nanowire formation | Kuo-Cheng Ching, Carlos H. Diaz | 2017-04-25 |
| 9620591 | Semiconductor structures and methods for multi-level work function and multi-valued channel doping of nanowire transistors to improve drive current | Tsung-Hsing Yu, Yeh Hsu, Chia-Wen Liu | 2017-04-11 |
| 9620422 | Semiconductor arrangement | Chung-Cheng Wu, Sang Hoo Dhong, Ta-Pen Guo | 2017-04-11 |
| 9614059 | Forming conductive STI liners for FinFETs | — | 2017-04-04 |
| 9614091 | Gate structure and method for fabricating the same | Ta-Pen Guo, Carlos H. Diaz | 2017-04-04 |
| 9570579 | Semiconductor structures and methods for multi-level work function | Carlos H. Diaz | 2017-02-14 |
| 9564493 | Devices having a semiconductor material that is semimetal in bulk and methods of forming the same | Carlos H. Diaz, Yee-Chia Yeo | 2017-02-07 |
| 9564431 | Semiconductor structures and methods for multi-level work function | Chia-Wen Liu, Wei-Hao Wu, Chih-Hao Wang, Carlos H. Diaz | 2017-02-07 |
| 9508858 | Contacts for highly scaled transistors | Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Chun-Hsiung Lin +2 more | 2016-11-29 |
| 9490348 | Method of forming a FinFET having an oxide region in the source/drain region | Kuo-Cheng Ching, Chih-Hao Wang, Ching-Wei Tsai, Zhiqiang Wu | 2016-11-08 |
| 9484460 | Semiconductor device having gate dielectric surrounding at least some of channel region and gate electrode surrounding at least some of gate dielectric | Tsung-Hsing Yu, Yeh Hsu, Chia-Wen Liu, Carlos H. Diaz | 2016-11-01 |
| 9478624 | Self-aligned wrapped-around structure | Kuo-Cheng Ching, Ta-Pen Guo, Carlos H. Diaz | 2016-10-25 |
| 9466668 | Inducing localized strain in vertical nanowire transistors | Gwan Sin Chang, Carlos H. Diaz | 2016-10-11 |
| 9425324 | Semiconductor device and channel structure thereof | Carlos H. Diaz | 2016-08-23 |
| 9419098 | Tuning strain in semiconductor devices | Kuo-Cheng Ching, Gwan Sin Chang, Zhiqiang Wu, Chih-Hao Wang, Carlos H. Diaz | 2016-08-16 |
| 9419003 | Semiconductor devices and methods of manufacture thereof | Carlos H. Diaz, Ta-Pen Guo | 2016-08-16 |
| 9412828 | Aligned gate-all-around structure | Kuo-Cheng Ching, Zhiqiang Wu | 2016-08-09 |
| 9368619 | Method for inducing strain in vertical semiconductor columns | Gwan Sin Chang, Carlos H. Diaz | 2016-06-14 |
| 9356020 | Semiconductor arrangement | Sang Hoo Dhong, Ta-Pen Guo, Chung-Cheng Wu | 2016-05-31 |
| 9349850 | Thermally tuning strain in semiconductor devices | Kuo-Cheng Ching, Gwan Sin Chang, Zhiqiang Wu, Chih-Hao Wang, Carlos H. Diaz | 2016-05-24 |