Issued Patents All Time
Showing 25 most recent of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12432960 | Wraparound contact with reduced distance to channel | Ruilong Xie, Reinaldo Vega, Yao Yao, Andrew M. Greene, Veeraraghavan S. Basker +2 more | 2025-09-30 |
| 12176404 | Wrap-around contact for nanosheet device | Ruilong Xie, Oleg Gluschenkov, Andrew M. Greene | 2024-12-24 |
| 11777034 | Hybrid complementary field effect transistor device | Ruilong Xie, Chen Zhang, Jingyun Zhang, Junli Wang | 2023-10-03 |
| 11575022 | Vertical field-effect transistor late gate recess process with improved inter-layer dielectric protection | Wenyu Xu, Ruilong Xie, Hemanth Jagannathan | 2023-02-07 |
| 11387319 | Nanosheet transistor device with bottom isolation | Ruilong Xie, Veeraraghavan S. Basker, Andrew M. Greene | 2022-07-12 |
| 11201089 | Robust low-k bottom spacer for VFET | Hiroaki Niimi, Kangguo Cheng | 2021-12-14 |
| 11183583 | Vertical transport FET with bottom source and drain extensions | Shogo Mochizuki | 2021-11-23 |
| 10937890 | Vertical field-effect transistor late gate recess process with improved inter-layer dielectric protection | Wenyu Xu, Ruilong Xie, Hemanth Jagannathan | 2021-03-02 |
| 10916627 | Nanosheet transistor with fully isolated source and drain regions and spacer pinch off | Nicolas Loubet | 2021-02-09 |
| 10790393 | Utilizing multilayer gate spacer to reduce erosion of semiconductor Fin during spacer patterning | Andrew M. Greene, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Eric R. Miller | 2020-09-29 |
| 10756203 | Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism | Julien Frougier, Ruilong Xie, Steven R. Bentley, Kangguo Cheng, Nicolas Loubet | 2020-08-25 |
| 10741675 | Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism | Julien Frougier, Ruilong Xie, Steven R. Bentley, Kangguo Cheng, Nicolas Loubet | 2020-08-11 |
| 10699965 | Removal of epitaxy defects in transistors | Andrew M. Greene, Ruilong Xie, Christopher M. Prindle | 2020-06-30 |
| 10636694 | Dielectric isolation in gate-all-around devices | Robin Hsin Kuo Chao, Kangguo Cheng, Nicolas Loubet, Ruilong Xie | 2020-04-28 |
| 10553705 | Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism | Julien Frougier, Ruilong Xie, Steven R. Bentley, Kangguo Cheng, Nicolas Loubet | 2020-02-04 |
| 10546945 | Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism | Julien Frougier, Ruilong Xie, Steven R. Bentley, Kangguo Cheng, Nicolas Loubet | 2020-01-28 |
| 10453736 | Dielectric isolation in gate-all-around devices | Robin Hsin Kuo Chao, Kangguo Cheng, Nicolas Loubet, Ruilong Xie | 2019-10-22 |
| 10431663 | Method of forming integrated circuit with gate-all-around field effect transistor and the resulting structure | Ruilong Xie, Balasubramanian Pranatharthiharan, Julien Frougier | 2019-10-01 |
| 10388760 | Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism | Julien Frougier, Ruilong Xie, Steven R. Bentley, Kangguo Cheng, Nicolas Loubet | 2019-08-20 |
| 10366931 | Nanosheet devices with CMOS epitaxy and method of forming | Ruilong Xie, Cheng Chi, Tenko Yamashita, Nicolas Loubet | 2019-07-30 |
| 10347749 | Reducing bending in parallel structures in semiconductor fabrication | Balasubramanian Pranatharthiharan, John R. Sporre, Ruilong Xie | 2019-07-09 |
| 10243079 | Utilizing multilayer gate spacer to reduce erosion of semiconductor fin during spacer patterning | Andrew M. Greene, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Eric R. Miller | 2019-03-26 |
| 10109722 | Etch-resistant spacer formation on gate structure | Ruilong Xie, Zhenxing Bi, Eric R. Miller, Balasubramanian Pranatharthiharan, Oleg Gluschenkov +2 more | 2018-10-23 |
| 10109533 | Nanosheet devices with CMOS epitaxy and method of forming | Ruilong Xie, Cheng Chi, Tenko Yamashita, Nicolas Loubet | 2018-10-23 |
| 10103245 | Embedded shape sige for strained channel transistors | John H. Zhang | 2018-10-16 |