Issued Patents All Time
Showing 25 most recent of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12374675 | Method of producing hybrid semiconductor wafer | Yunlong Li, Luc Haspeslagh, Philippe Soussan, Deniz Sabuncuoglu Tezcan | 2025-07-29 |
| 12334398 | Multilayer dielectric stack for damascene top-via integration | Sagarika Mukesh, Devika Sarkar Grant, Fee Li Lie, Shravan Kumar Matham, Hosadurga Shobha | 2025-06-17 |
| 12327798 | Physical unclonable function | Kangguo Cheng, Eric R. Miller, Fee Li Lie, Marc A. Bergendahl, John R. Sporre | 2025-06-10 |
| RE50174 | Structure and process to tuck fin tips self-aligned to gates | Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Fee Li Lie, Derrick Liu +2 more | 2024-10-15 |
| 12086528 | Secure fingerprinting of a trusted photomask | Scott D. Halle, Effendi Leobandung, Gangadhara Raja Muthinti, Ravi K. Bonam | 2024-09-10 |
| 11869936 | Semiconductor device and method of forming the semiconductor device | Marc A. Bergendahl, Fee Li Lie, Eric R. Miller, Robert R. Robison, John R. Sporre +1 more | 2024-01-09 |
| 11869937 | Semiconductor device and method of forming the semiconductor device | Marc A. Bergendahl, Fee Li Lie, Eric R. Miller, Robert R. Robison, John R. Sporre +1 more | 2024-01-09 |
| 11673766 | Elevator analytics facilitating passenger destination prediction and resource optimization | Tara Astigarraga, Eric R. Miller, Kangguo Cheng, Fee Li Lie, Sean Teehan +1 more | 2023-06-13 |
| 11615992 | Substrate isolated VTFET devices | Eric R. Miller, Marc A. Bergendahl, Kangguo Cheng, John R. Sporre, Fee Li Lie | 2023-03-28 |
| 11462631 | Sublithography gate cut physical unclonable function | Kangguo Cheng, Eric R. Miller, Fee Li Lie, Marc A. Bergendahl, John R. Sporre | 2022-10-04 |
| 11398377 | Bilayer hardmask for direct print lithography | Praveen Joseph, Yann Mignot | 2022-07-26 |
| 11239316 | Semiconductor device and method of forming the semiconductor device | Marc A. Bergendahl, Fee Li Lie, Eric R. Miller, Robert R. Robison, John R. Sporre +1 more | 2022-02-01 |
| 11182722 | Cognitive system for automatic risk assessment, solution identification, and action enablement | Alex Richard Hubbard, Spyridon Skordas, Marc A. Bergendahl, Cody J. Murray, Lawrence A. Clevenger | 2021-11-23 |
| 11127815 | Semiconductor device and method of forming the semiconductor device | Marc A. Bergendahl, Fee Li Lie, Eric R. Miller, Robert R. Robison, John R. Sporre +1 more | 2021-09-21 |
| 11075299 | Transistor gate having tapered segments positioned above the fin channel | Eric R. Miller, Marc A. Bergendahl, Fee Li Lie, Kangguo Cheng, Sean Teehan | 2021-07-27 |
| 11043494 | Structure and method for equal substrate to channel height between N and P fin-FETs | Lawrence A. Clevenger, Leigh Anne H. Clevenger, Mona A. Ebrish, Fee Li Lie, Deepika Priyadarshini +2 more | 2021-06-22 |
| 10964812 | Integration of input/output device in vertical field-effect transistor technology | Xuefeng Liu, Junli Wang, Brent A. Anderson, Terence B. Hook | 2021-03-30 |
| 10937810 | Sub-fin removal for SOI like isolation with uniform active fin height | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre +1 more | 2021-03-02 |
| 10840373 | Integration of input/output device in vertical field-effect transistor technology | Xuefeng Liu, Junli Wang, Brent A. Anderson, Terence B. Hook | 2020-11-17 |
| 10832945 | Techniques to improve critical dimension width and depth uniformity between features with different layout densities | Nicole Saulnier, Indira Seshadri, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Fee Li Lie +3 more | 2020-11-10 |
| 10833190 | Super long channel device within VFET architecture | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre +1 more | 2020-11-10 |
| 10818751 | Nanosheet transistor barrier for electrically isolating the substrate from the source or drain regions | Mona A. Ebrish, Fee Li Lie, Nicolas Loubet, Indira Seshadri, Lawrence A. Clevenger +1 more | 2020-10-27 |
| 10790393 | Utilizing multilayer gate spacer to reduce erosion of semiconductor Fin during spacer patterning | Andrew M. Greene, Hong He, Sivananda K. Kanakasabapathy, Eric R. Miller, Pietro Montanini | 2020-09-29 |
| 10734523 | Nanosheet substrate to source/drain isolation | Fee Li Lie, Mona A. Ebrish, Ekmini Anuja De Silva, Indira Seshadri, Lawrence A. Clevenger +2 more | 2020-08-04 |
| 10727273 | Magnetoresistive random access memory thin film transistor unit cell | Praveen Joseph, Xuefeng Liu, Eric Raymond Evarts | 2020-07-28 |