Issued Patents All Time
Showing 26–50 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10622250 | Dielectric gap fill evaluation for integrated circuits | Isabel Cristina Chu, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Ekmini Anuja De Silva, Fee Li Lie +3 more | 2020-04-14 |
| 10615276 | Integration of input/output device in vertical field-effect transistor technology | Xuefeng Liu, Junli Wang, Brent A. Anderson, Terence B. Hook | 2020-04-07 |
| 10615278 | Preventing strained fin relaxation | Kangguo Cheng, Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Juntao Li +3 more | 2020-04-07 |
| 10573745 | Super long channel device within VFET architecture | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre +1 more | 2020-02-25 |
| 10438972 | Sub-fin removal for SOI like isolation with uniform active fin height | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre +1 more | 2019-10-08 |
| 10424663 | Super long channel device within VFET architecture | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre +1 more | 2019-09-24 |
| 10381437 | Semiconductor device and method of forming the semiconductor device | Marc A. Bergendahl, Fee Li Lie, Eric R. Miller, Robert R. Robison, John R. Sporre +1 more | 2019-08-13 |
| 10381348 | Structure and method for equal substrate to channel height between N and P fin-FETs | Lawrence A. Clevenger, Leigh Anne H. Clevenger, Mona A. Ebrish, Fee Li Lie, Deepika Priyadarshini +2 more | 2019-08-13 |
| 10361127 | Vertical transport FET with two or more gate lengths | Fee Li Lie, Indira Seshadri, Mona A. Ebrish, Leigh Anne H. Clevenger, Ekmini Anuja De Silva +1 more | 2019-07-23 |
| 10312140 | Dielectric gap fill evaluation for integrated circuits | Isabel Cristina Chu, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Ekmini Anuja De Silva, Fee Li Lie +3 more | 2019-06-04 |
| 10304689 | Margin for fin cut using self-aligned triple patterning | Fee Li Lie, Eric R. Miller, Stuart A. Sieg, John R. Sporre, Sean Teehan | 2019-05-28 |
| 10243079 | Utilizing multilayer gate spacer to reduce erosion of semiconductor fin during spacer patterning | Andrew M. Greene, Hong He, Sivananda K. Kanakasabapathy, Eric R. Miller, Pietro Montanini | 2019-03-26 |
| 10229910 | Separate N and P fin etching for reduced CMOS device leakage | Isabel Cristina Chu, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Mona A. Ebrish, Fee Li Lie +3 more | 2019-03-12 |
| 10211321 | Stress retention in fins of fin field-effect transistors | Sivananda K. Kanakasabapathy, Juntao Li, Fee Li Lie, Stuart A. Sieg, John R. Sporre | 2019-02-19 |
| 10211319 | Stress retention in fins of fin field-effect transistors | Sivananda K. Kanakasabapathy, Juntao Li, Fee Li Lie, Stuart A. Sieg, John R. Sporre | 2019-02-19 |
| 10199503 | Under-channel gate transistors | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre +1 more | 2019-02-05 |
| 10170477 | Forming MOSFET structures with work function modification | Ruqiang Bao, Derrick Liu, Robert R. Robison, Gen Tsutsui, Reinaldo Vega +1 more | 2019-01-01 |
| 10147725 | Forming MOSFET structures with work function modification | Ruqiang Bao, Derrick Liu, Robert R. Robison, Gen Tsutsui, Reinaldo Vega +1 more | 2018-12-04 |
| 10121852 | Structure and process to tuck fin tips self-aligned to gates | Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Fee Li Lie, Derrick Liu +2 more | 2018-11-06 |
| 10121853 | Structure and process to tuck fin tips self-aligned to gates | Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Fee Li Lie, Derrick Liu +2 more | 2018-11-06 |
| 10062714 | FinFET device having a high germanium content fin structure and method of making same | Bruce B. Doris, Qing Liu | 2018-08-28 |
| 10032680 | Strained finFET device fabrication | Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Fee Li Lie, Stuart A. Sieg | 2018-07-24 |
| 10032885 | Channel replacement and bimodal doping scheme for bulk finFet threshold voltage modulation with reduced performance penalty | Robert R. Robison, Reinaldo Vega | 2018-07-24 |
| 9997369 | Margin for fin cut using self-aligned triple patterning | Fee Li Lie, Eric R. Miller, Stuart A. Sieg, John R. Sporre, Sean Teehan | 2018-06-12 |
| 9917019 | Strained FinFET device fabrication | Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Fee Li Lie, Stuart A. Sieg | 2018-03-13 |