Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Walid M. Hafez — 169 Patents

Intel: 167 patents #80 of 30,777Top 1%
TRTahoe Research: 1 patents #81 of 215Top 40%
Portland, OR: #39 of 9,213 inventorsTop 1%
Oregon: #79 of 28,073 inventorsTop 1%
Overall (All Time): #4,849 of 4,157,543Top 1%
169 Patents All Time
Walid M. Hafez has been granted 169 US patents while listed as an inventor at Intel. The first was granted in 2011 and the most recent in October 2025. Walid M. Hafez ranks #4,849 of 4,157,543 US inventors in our database (top 0.12%). Patent records list Walid M. Hafez in Portland, OR, US.

Issued Patents All Time

Showing 1–25 of 169 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12453145 Single gated 3D nanowire inverter for high density thick gate SoC applications Ramachandran Ramaswamy, Tanuj Trivedi, Jeenok T. Kim, Ting Chang, Babak Fallahazad +2 more 2025-10-21
12389626 High-voltage transistor with self-aligned isolation Chia-Hong Jan 2025-08-12
12369358 Co-integrated high performance nanoribbon transistors with high voltage thick gate finFET devices Tanuj Trivedi, Rahul Ramaswamy, Jeong Dong Kim, Ting Chang, Babak Fallahazad +2 more 2025-07-22
12349411 Gate-all-around integrated circuit structures having dual nanoribbon channel structures Tanuj Trivedi, Rahul Ramaswamy, Jeong Dong Kim, Babak Fallahazad, Hsu-Yu Chang +2 more 2025-07-01
12317585 Adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions Sairam Subramanian, Hsu-Yu Chang, Chia-Hong Jan, Tanuj Trivedi 2025-05-27
12249622 Nanoribbon thick gate devices with differential ribbon spacing and width for SOC applications Tanuj Trivedi, Rahul Ramaswamy, Jeong Dong Kim, Ting Chang, Babak Fallahazad +2 more 2025-03-11
12199101 Self-aligned gate endcap (SAGE) architecture having gate contacts Sairam Subramanian 2025-01-14
12191207 Non-planar I/O and logic semiconductor devices having different workfunction on common substrate Roman W. Olac-Vaw, Chia-Hong Jan, Pei-Chi Liu 2025-01-07
12148757 Integration of Si-based transistors with non-Si technologies by semiconductor regrowth over an insulator material Nidhi Nidhi, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer +2 more 2024-11-19 $25,575,000
12136628 High voltage three-dimensional devices having dielectric liners Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti 2024-11-05 $48,202,000
12108595 Integrated fuse in self-aligned gate endcap for FinFET architectures and methods of fabrication Sumit Ashtekar, Rahul Ramaswamy, Hector M. Saavedra Garcia 2024-10-01 $20,560,000
12089411 Self-aligned front-end charge trap flash memory cell and capacitor design for integrated high-density scaled devices Tanuj Trivedi, Rohan K. Bambery, Daniel B. O'Brien, Christopher Alan Nolph, Rahul Ramaswamy +1 more 2024-09-10 $16,964,000
12080763 Silicide for group III-nitride devices and methods of fabrication Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Paul B. Fischer 2024-09-03 $14,017,000
12040395 High voltage extended-drain MOS (EDMOS) nanowire transistors Nidhi Nidhi, Rahul Ramaswamy, Hsu-Yu Chang, Ting Chang, Babak Fallahazad +2 more 2024-07-16 $26,089,000
12027613 III-N transistor arrangements for reducing nonlinearity of off-state capacitance Nidhi Nidhi, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer +2 more 2024-07-02 $27,114,000
11996403 ESD diode solution for nanoribbon architectures Nidhi Nidhi, Rahul Ramaswamy, Hsu-Yu Chang, Ting Chang, Babak Fallahazad +4 more 2024-05-28 $30,739,000
11967615 Dual threshold voltage (VT) channel devices and their methods of fabrication Hsu-Yu Chang, Neville L. Dias, Chia-Hong Jan, Roman W. Olac-Vaw, Chen-Guan Lee 2024-04-23 $40,668,000
11935892 Self-aligned gate endcap (SAGE) architecture having gate contacts Sairam Subramanian 2024-03-19 $28,784,000
11881511 Superlattice FINFET with tunable drive current capability Nidhi Nidhi, Rahul Ramaswamy, Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic +2 more 2024-01-23 $52,361,000
11881486 High voltage three-dimensional devices having dielectric liners Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti 2024-01-23 $52,361,000
11876121 Self-aligned gate endcap (SAGE) architecture having gate or contact plugs Sairam Subramanian 2024-01-16 $42,805,000
11862703 Gate-all-around integrated circuit structures having dual nanoribbon channel structures Tanuj Trivedi, Rahul Ramaswamy, Jeong Dong Kim, Babak Fallahazad, Hsu-Yu Chang +2 more 2024-01-02 $30,016,000
11848362 III-N transistors with contacts of modified widths Rahul Ramaswamy, Nidhi Nidhi, Johann Christian Rode, Han Wui Then, Marko Radosavljevic +1 more 2023-12-19 $50,836,000
11823954 Non-planar I/O and logic semiconductor devices having different workfunction on common substrate Roman W. Olac-Vaw, Chia-Hong Jan, Pei-Chi Liu 2023-11-21 $28,968,000
11824002 Variable pitch and stack height for high performance interconnects En-Shao Liu, Joodong Park, Chen-Guan Lee, Chia-Hong Jan, Jiansheng Xu 2023-11-21 $28,968,000