Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12369358 | Co-integrated high performance nanoribbon transistors with high voltage thick gate finFET devices | Tanuj Trivedi, Rahul Ramaswamy, Jeong Dong Kim, Walid M. Hafez, Babak Fallahazad +2 more | 2025-07-22 |
| 12349411 | Gate-all-around integrated circuit structures having dual nanoribbon channel structures | Tanuj Trivedi, Rahul Ramaswamy, Jeong Dong Kim, Babak Fallahazad, Hsu-Yu Chang +2 more | 2025-07-01 |
| 12249622 | Nanoribbon thick gate devices with differential ribbon spacing and width for SOC applications | Tanuj Trivedi, Rahul Ramaswamy, Jeong Dong Kim, Walid M. Hafez, Babak Fallahazad +2 more | 2025-03-11 |
| 12089411 | Self-aligned front-end charge trap flash memory cell and capacitor design for integrated high-density scaled devices | Tanuj Trivedi, Walid M. Hafez, Rohan K. Bambery, Daniel B. O'Brien, Christopher Alan Nolph +1 more | 2024-09-10 |
| 12040395 | High voltage extended-drain MOS (EDMOS) nanowire transistors | Nidhi Nidhi, Rahul Ramaswamy, Walid M. Hafez, Hsu-Yu Chang, Babak Fallahazad +2 more | 2024-07-16 |
| 11996403 | ESD diode solution for nanoribbon architectures | Nidhi Nidhi, Rahul Ramaswamy, Walid M. Hafez, Hsu-Yu Chang, Babak Fallahazad +4 more | 2024-05-28 |
| 11862703 | Gate-all-around integrated circuit structures having dual nanoribbon channel structures | Tanuj Trivedi, Rahul Ramaswamy, Jeong Dong Kim, Babak Fallahazad, Hsu-Yu Chang +2 more | 2024-01-02 |
| 11791380 | Single gated 3D nanowire inverter for high density thick gate SOC applications | Rahul Ramaswamy, Walid M. Hafez, Tanuj Trivedi, Jeong Dong Kim, Babak Fallahazad +2 more | 2023-10-17 |
| 11581404 | Gate-all-around integrated circuit structures having depopulated channel structures | Tanuj Trivedi, Jeong Dong Kim, Walid M. Hafez, Hsu-Yu Chang, Rahul Ramaswamy +1 more | 2023-02-14 |
| 11437483 | Gate-all-around integrated circuit structures having dual nanoribbon channel structures | Tanuj Trivedi, Rahul Ramaswamy, Jeong Dong Kim, Babak Fallahazad, Hsu-Yu Chang +2 more | 2022-09-06 |
| 11094782 | Gate-all-around integrated circuit structures having depopulated channel structures | Tanuj Trivedi, Jeong Dong Kim, Walid M. Hafez, Hsu-Yu Chang, Rahul Ramaswamy +1 more | 2021-08-17 |
| 10847456 | Antifuse element using spacer breakdown | Chia-Hong Jan, Walid M. Hafez | 2020-11-24 |
| 10763209 | MOS antifuse with void-accelerated breakdown | Roman W. Olac-Vaw, Walid M. Hafez, Chia-Hong Jan, Hsu-Yu Chang, Rahul Ramaswamy +2 more | 2020-09-01 |
| 10312367 | Monolithic integration of high voltage transistors and low voltage non-planar transistors | Kinyip Phoa, Nidhi Nidhi, Chia-Hong Jan | 2019-06-04 |
| 10192969 | Transistor gate metal with laterally graduated work function | Chia-Hong Jan, Walid M. Hafez, Hsu-Yu Chang, Roman W. Olac-Vaw, Rahul Ramaswamy +2 more | 2019-01-29 |
| 10164115 | Non-linear fin-based devices | Neville L. Dias, Chia-Hong Jan, Walid M. Hafez, Roman W. Olac-Vaw, Hsu-Yu Chang +2 more | 2018-12-25 |
| 9929090 | Antifuse element using spacer breakdown | Chia-Hong Jan, Walid M. Hafez | 2018-03-27 |
| 9799668 | Memory cell having isolated charge sites and method of fabricating same | Chia-Hong Jan, Walid M. Hafez | 2017-10-24 |
| 6810500 | Method for mapping a two-dimensional data array in a memory | — | 2004-10-26 |