Issued Patents All Time
Showing 26–50 of 168 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11791257 | Device terminal interconnect structures | Sairam Subramanian | 2023-10-17 |
| 11764260 | Dielectric and isolation lower fin material for fin-based electronics | Chia-Hong Jan | 2023-09-19 |
| 11757027 | E-D mode 2DEG FET with gate spacer to locally tune VT and improve breakdown | Rahul Ramaswamy, Nidhi Nidhi, Johann Christian Rode, Paul B. Fischer, Han Wui Then +2 more | 2023-09-12 |
| 11715790 | Charge-induced threshold voltage tuning in III-N transistors | Nidhi Nidhi, Marko Radosavljevic, Sansaptak Dasgupta, Yang Cao, Han Wui Then +3 more | 2023-08-01 |
| 11715737 | Metal fuse and self-aligned gate edge (SAGE) architecture having a metal fuse | Rohan K. Bambery, Mong-Kai Wu | 2023-08-01 |
| 11705453 | Self-aligned gate endcap (SAGE) architecture having local interconnects | Sairam Subramanian, Sridhar Govindaraju, Kiran CHIKKADI | 2023-07-18 |
| 11695008 | Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process | Curtis Tsai, Chia-Hong Jan, Jeng-Ya David Yeh, Joodong Park | 2023-07-04 |
| 11688792 | Dual self-aligned gate endcap (SAGE) architectures | Sairam Subramanian, Sridhar Govindaraju, Mark Liu, Szuya S. Liao, Chia-Hong Jan +2 more | 2023-06-27 |
| 11688788 | Transistor gate structure with hybrid stacks of dielectric material | Johann Christian Rode, Samuel J. Beach, Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then | 2023-06-27 |
| 11670709 | III-N transistors with local stressors for threshold voltage control | Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Nidhi Nidhi, Rahul Ramaswamy +2 more | 2023-06-06 |
| 11670637 | Logic circuit with indium nitride quantum well | Marko Radosavljevic, Sansaptak Dasgupta, Han Wui Then, Paul B. Fischer | 2023-06-06 |
| 11664417 | III-N metal-insulator-semiconductor field effect transistors with multiple gate dielectric materials | Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Paul B. Fischer | 2023-05-30 |
| 11658217 | Transistors with ion- or fixed charge-based field plate structures | Han Wui Then, Marko Radosavljevic, Glenn A. Glass, Sansaptak Dasgupta, Nidhi Nidhi +3 more | 2023-05-23 |
| 11652143 | III-N transistors integrated with thin-film transistors having graded dopant concentrations and/or composite gate dielectrics | Han Wui Then, Nidhi Nidhi, Paul B. Fischer, Rahul Ramaswamy, Samuel J. Beach +4 more | 2023-05-16 |
| 11626513 | Antenna gate field plate on 2DEG planar FET | Rahul Ramaswamy, Nidhi Nidhi, Johann Christian Rode, Paul B. Fischer, Han Wui Then +3 more | 2023-04-11 |
| 11610971 | Cap layer on a polarization layer to preserve channel sheet resistance | Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Nidhi Nidhi, Rahul Ramaswamy +2 more | 2023-03-21 |
| 11610917 | High voltage three-dimensional devices having dielectric liners | Jeng-Ya David Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti | 2023-03-21 |
| 11610887 | Side-by-side integration of III-n transistors and thin-film transistors | Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer | 2023-03-21 |
| 11605632 | Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls | Sridhar Govindaraju, Mark Liu, Szuya S. Liao, Chia-Hong Jan, Nick Lindert +2 more | 2023-03-14 |
| 11588037 | Planar transistors with wrap-around gates and wrap-around source and drain contacts | Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta +2 more | 2023-02-21 |
| 11587924 | Integration of passive components in III-N devices | Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then, Marko Radosavljevic, Johann Christian Rode +1 more | 2023-02-21 |
| 11581404 | Gate-all-around integrated circuit structures having depopulated channel structures | Tanuj Trivedi, Jeong Dong Kim, Hsu-Yu Chang, Rahul Ramaswamy, Ting Chang +1 more | 2023-02-14 |
| 11581313 | Integration of III-N transistors and non-III-N transistors by semiconductor regrowth | Sansaptak Dasgupta, Johann Christian Rode, Han Wui Then, Marko Radosavljevic, Paul B. Fischer +3 more | 2023-02-14 |
| 11563000 | Gate endcap architectures having relatively short vertical stack | Sairam Subramanian, Hsu-Yu Chang, Chia-Hong Jan | 2023-01-24 |
| 11562999 | Cost effective precision resistor using blocked DEPOP method in self-aligned gate endcap (SAGE) architecture | Roman W. Olac-Vaw, Nick Lindert, Chia-Hong Jan | 2023-01-24 |