SG

Sridhar Govindaraju

IN Intel: 18 patents #2,286 of 30,777Top 8%
Overall (All Time): #249,448 of 4,157,543Top 6%
18
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12094780 Techniques and configurations to reduce transistor gate short defects Matthew J. Prince 2024-09-17
11978776 Non-planar semiconductor device having conforming ohmic contacts Ashutosh Sagar 2024-05-07
11756833 Techniques and configurations to reduce transistor gate short defects Matthew J. Prince 2023-09-12
11705453 Self-aligned gate endcap (SAGE) architecture having local interconnects Sairam Subramanian, Walid M. Hafez, Kiran CHIKKADI 2023-07-18
11688792 Dual self-aligned gate endcap (SAGE) architectures Sairam Subramanian, Walid M. Hafez, Mark Liu, Szuya S. Liao, Chia-Hong Jan +2 more 2023-06-27
11605632 Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls Walid M. Hafez, Mark Liu, Szuya S. Liao, Chia-Hong Jan, Nick Lindert +2 more 2023-03-14
11380592 Techniques and configurations to reduce transistor gate short defects Matthew J. Prince 2022-07-05
11329138 Self-aligned gate endcap (SAGE) architecture having endcap plugs Sairam Subramanian, Christopher KENYON, Chia-Hong Jan, Mark Liu, Szuya S. Liao +1 more 2022-05-10
11217582 Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls Walid M. Hafez, Mark Liu, Szuya S. Liao, Chia-Hong Jan, Nick Lindert +2 more 2022-01-04
11205708 Dual self-aligned gate endcap (SAGE) architectures Sairam Subramanian, Walid M. Hafez, Mark Liu, Szuya S. Liao, Chia-Hong Jan +2 more 2021-12-21
10847423 Techniques and configurations to reduce transistor gate short defects Matthew J. Prince 2020-11-24
10468305 Techniques and configurations to reduce transistor gate short defects Matthew J. Prince 2019-11-05
9761497 Techniques and configurations to reduce transistor gate short defects Matthew J. Prince 2017-09-12
9704798 Using materials with different etch rates to fill trenches in semiconductor devices Anindya Dasgupta, Rohit Grover 2017-07-11
9281401 Techniques and configurations to reduce transistor gate short defects Matthew J. Prince 2016-03-08
7892971 Sub-second annealing processes for semiconductor devices Jack Hwang, Karson Knutson, Harold W. Kennel, Aravind S. Killampalli 2011-02-22
7790587 Method to reduce junction leakage through partial regrowth with ultrafast anneal and structures formed thereby Jack Hwang, Seok Hee Lee, Patrick H. Keys, Chad D. Lindfors 2010-09-07
7758238 Temperature measurement with reduced extraneous infrared in a processing chamber Karson Knutson, Harold W. Kennel, Aravind S. Killampalli, Jack Hwang 2010-07-20