Issued Patents All Time
Showing 25 most recent of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6449692 | Microprocessor circuits, systems, and methods with combined on-chip pixel and non-pixel cache structure | Steven D. Krueger, Ian Chen | 2002-09-10 |
| 6442667 | Selectively powering X Y organized memory banks | Donald E. Steiss | 2002-08-27 |
| 6412107 | Method and system of providing dynamic optimization information in a code interpretive runtime environment | Robert J. Cyran, Paul Knueven | 2002-06-25 |
| 6408320 | Instruction set architecture with versatile adder carry control | — | 2002-06-18 |
| 6401212 | Microprocessor circuits, systems, and methods for conditioning information prefetching based on resource burden | James O. Bondi | 2002-06-04 |
| 6338137 | Data processor having memory access unit with predetermined number of instruction cycles between activation and initial data transfer | Patrick W. Bosshart | 2002-01-08 |
| 6317820 | Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism | David H. Bartley | 2001-11-13 |
| 6216219 | Microprocessor circuits, systems, and methods implementing a load target buffer with entries relating to prefetch desirability | George Cai | 2001-04-10 |
| 6212601 | Microprocessor system with block move circuit disposed between cache circuits | — | 2001-04-03 |
| 6209114 | Efficient hardware implementation of chien search polynomial reduction in reed-solomon decoding | Tod D. Wolf | 2001-03-27 |
| 6195735 | Prefetch circuity for prefetching variable size data | Steven D. Krueger | 2001-02-27 |
| 6178481 | Microprocessor circuits and systems with life spanned storage circuit for storing non-cacheable data | Steven D. Krueger | 2001-01-23 |
| 6173368 | Class categorized storage circuit for storing non-cacheable data until receipt of a corresponding terminate signal | Steven D. Krueger | 2001-01-09 |
| 6173410 | Microprocessor circuits, systems and methods for conditioning information prefetching based on resource burden | James O. Bondi | 2001-01-09 |
| 6170053 | Microprocessor with circuits, systems and methods for responding to branch instructions based on history of prediction accuracy | Timothy David Anderson, Simonjit Dutta | 2001-01-02 |
| 6138232 | Microprocessor with rate of instruction operation dependent upon interrupt source for power consumption control | Robert Marshall | 2000-10-24 |
| 6134634 | Method and apparatus for preemptive cache write-back | Robert Marshall | 2000-10-17 |
| 6119222 | Combined branch prediction and cache prefetch in a microprocessor | James O. Bondi | 2000-09-12 |
| 6108775 | Dynamically loadable pattern history tables in a multi-task microprocessor | George Cai | 2000-08-22 |
| 6085269 | Configurable expansion bus controller in a microprocessor-based system | Tai-Yuen CHAN, Steven D. Krueger | 2000-07-04 |
| 6064254 | High speed integrated circuit interconnection having proximally located active converter | Wilbur C. Vogley | 2000-05-16 |
| 6065113 | Circuits, systems, and methods for uniquely identifying a microprocessor at the instruction set level employing one-time programmable register | Joel J. Graber, Donald E. Steiss | 2000-05-16 |
| 6065125 | SMM power management circuits, systems, and methods | Ian Chen | 2000-05-16 |
| 6049672 | Microprocessor with circuits, systems, and methods for operating with patch micro-operation codes and patch microinstruction codes stored in multi-purpose memory structure | Patrick W. Bosshart | 2000-04-11 |
| 6041176 | Emulation devices utilizing state machines | — | 2000-03-21 |