Issued Patents All Time
Showing 25 most recent of 294 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423481 | Secure master and secure guest endpoint security firewall | Joseph Zbiciak, Matthew D. Pierson, Kai Chirca | 2025-09-23 |
| 12417186 | Write merging on stores with different tags | Naveen Bhoria, Pete Michael Hippleheuser | 2025-09-16 |
| 12393521 | Methods and apparatus to facilitate write miss caching in cache system | Naveen Bhoria, Pete Michael Hippleheuser | 2025-08-19 |
| 12386623 | Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor | Duc Quang Bui, Joseph Zbiciak | 2025-08-12 |
| 12386696 | Delayed snoop for improved multi-process false sharing parallel thread performance | Kai Chirca | 2025-08-12 |
| 12380035 | Methods and apparatus to facilitate read-modify-write support in a coherent victim cache with parallel data paths | Naveen Bhoria, Pete Michael Hippleheuser | 2025-08-05 |
| 12379850 | Memory controller with command reordering | — | 2025-08-05 |
| 12373515 | Computational primitives using a matrix multiplication accelerator | Arthur John Redfern, Kai Chirca, Chenchi Luo, Zhenhua Yu | 2025-07-29 |
| 12373242 | Entering protected pipeline mode without annulling pending instructions | Duc Quang Bui | 2025-07-29 |
| 12367150 | Streaming engine with early and late address and loop count registers to track architectural state | Joseph Zbiciak | 2025-07-22 |
| 12366906 | Controlling the number of powered vector lanes via a register field | Duc Quang Bui | 2025-07-22 |
| 12360843 | Multicore shared cache operation engine | Kai Chirca, Joseph Zbiciak, David E. Smith, Matthew D. Pierson | 2025-07-15 |
| 12341534 | Butterfly network on load data return | Dheera Balasubramanian, Joseph Zbiciak, Duc Quang Bui | 2025-06-24 |
| 12333284 | Nested loop control | Kai Chirca, Todd T. Hahn, Alan L. Davis | 2025-06-17 |
| 12321284 | Methods and apparatus to facilitate atomic operations in victim cache | Naveen Bhoria, Pete Michael Hippleheuser | 2025-06-03 |
| 12321750 | Entering protected pipeline mode with clearing | Joseph Zbiciak, Duc Quang Bui, Mel Alan Phipps, Todd T. Hahn | 2025-06-03 |
| 12321285 | Victim cache with write miss merging | Naveen Bhoria, Pete Michael Hippleheuser | 2025-06-03 |
| 12314187 | Software-hardware memory management modes | Joseph Zbiciak, Kai Chirca, Daniel Wu | 2025-05-27 |
| 12307251 | Vector reverse | Duc Quang Bui | 2025-05-20 |
| 12299446 | Streaming engine with stream metadata saving for context switching | Joseph Zbiciak | 2025-05-13 |
| 12292839 | Write merging on stores with different privilege levels | Naveen Bhoria, Pete Michael Hippleheuser | 2025-05-06 |
| 12265827 | Forming constant extensions in the same execute packet in a VLIW processor | Duc Quang Bui, Joseph Zbiciak | 2025-04-01 |
| 12265477 | Hybrid victim cache and write miss buffer with fence operation | Naveen Bhoria, Pete Michael Hippleheuser | 2025-04-01 |
| 12259826 | Methods and apparatus for multi-banked victim cache with dual datapath | Naveen Bhoria, Pete Michael Hippleheuser | 2025-03-25 |
| 12260219 | Multiple instruction set architectures on a processing device | Duc Quang Bui, Paul Daniel Gauvreau | 2025-03-25 |