DW

Daniel Wu

TI Texas Instruments: 43 patents #191 of 12,488Top 2%
AM Amazon: 2 patents #7,121 of 19,158Top 40%
SN Siemens Information And Communication Networks: 1 patents #104 of 240Top 45%
Overall (All Time): #61,536 of 4,157,543Top 2%
46
Patents All Time

Issued Patents All Time

Showing 25 most recent of 46 patents

Patent #TitleCo-InventorsDate
12430201 Multi-processor bridge with cache allocate awareness Kai Chirca, Matthew D. Pierson 2025-09-30
12360844 Credit aware central arbitration for multi-endpoint, multi-core system Matthew D. Pierson, Kai Chirca 2025-07-15
12353336 Multichannel memory arbitration and interleaving scheme Abhishek Shankar, Mihir Narendra Mody, Gregory Raymond Shurtz, Jason A. T. Jones, Hemant Hariyani 2025-07-08
12314187 Software-hardware memory management modes Timothy David Anderson, Joseph Zbiciak, Kai Chirca 2025-05-27
12242392 Methods and apparatus to estimate consumed memory bandwidth Patrick Kruse, Gregory Raymond Shurtz, Denis Beaudoin, Abhishek Shankar 2025-03-04
12210454 Data storage interface layer with access and transformation management Sachin Suresh Bhat, Lionel Bitoun, LiJing Chen, Jaikit Savla, Jaden Wright +11 more 2025-01-28
12210459 Non-stalling, non-blocking translation lookaside buffer invalidation 2025-01-28
12182398 Virtual network pre-arbitration for deadlock avoidance and enhanced performance Matthew D. Pierson, Kai Chirca 2024-12-31
12079471 Adaptive credit-based replenishment threshold used for transaction arbitration in a system that supports multiple levels of credit expenditure 2024-09-03
12072812 Highly integrated scalable, flexible DSP megamodule architecture Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca +3 more 2024-08-27
12050914 Cache management operations using streaming engine Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Abhijeet Ashok Chachad +1 more 2024-07-30
12001282 Write control for read-modify-write operations in cache memory Abhijeet Ashok Chachad, Timothy David Anderson, David Matthew Thompson 2024-06-04
11960416 Multichannel memory arbitration and interleaving scheme Abhishek Shankar, Mihir Narendra Mody, Gregory Raymond Shurtz, Jason A. T. Jones, Hemant Hariyani 2024-04-16
11954044 Translation lookaside buffer prewarming 2024-04-09
11907528 Multi-processor bridge with cache allocate awareness Kai Chirca, Matthew D. Pierson 2024-02-20
11853225 Software-hardware memory management modes Timothy David Anderson, Joseph Zbiciak, Kai Chirca 2023-12-26
11687238 Virtual network pre-arbitration for deadlock avoidance and enhanced performance Matthew D. Pierson, Kai Chirca 2023-06-27
11663141 Non-stalling, non-blocking translation lookaside buffer invalidation 2023-05-30
11609818 Pipelined read-modify-write operations in cache memory Abhijeet Ashok Chachad, David Matthew Thompson 2023-03-21
11487442 Data storage interface for protocol-agnostic storage services Sachin Suresh Bhat, Lionel Bitoun, LiJing Chen, Jaikit Savla, Jaden Wright +11 more 2022-11-01
11487616 Write control for read-modify-write operations in cache memory Abhijeet Ashok Chachad, Timothy David Anderson, David Matthew Thompson 2022-11-01
11429527 Adaptive credit-based replenishment threshold used for transaction arbitration in a system that supports multiple levels of credit expenditure 2022-08-30
11429526 Credit aware central arbitration for multi-endpoint, multi-core system Matthew D. Pierson, Kai Chirca 2022-08-30
11347644 Distributed error detection and correction with hamming code handoff Kai Chirca, Matthew D. Pierson 2022-05-31
11307858 Cache preload operations using streaming engine Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Abhijeet Ashok Chachad +1 more 2022-04-19