Issued Patents All Time
Showing 26–46 of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11237905 | Pipelined read-modify-write operations in cache memory | Abhijeet Ashok Chachad, David Matthew Thompson | 2022-02-01 |
| 11119776 | Cache management operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Abhijeet Ashok Chachad +1 more | 2021-09-14 |
| 11099994 | Virtual network pre-arbitration for deadlock avoidance and enhanced performance | Matthew D. Pierson, Kai Chirca | 2021-08-24 |
| 11099993 | Multi-processor bridge with cache allocate awareness | Kai Chirca, Matthew D. Pierson | 2021-08-24 |
| 11036648 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca +3 more | 2021-06-15 |
| 10990529 | Multi-power-domain bridge with prefetch and write merging | Kai Chirca, Matthew D. Pierson | 2021-04-27 |
| 10802974 | Virtual network pre-arbitration for deadlock avoidance and enhanced performance | Matthew D. Pierson, Kai Chirca | 2020-10-13 |
| 10606596 | Cache preload operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Abhijeet Ashok Chachad +1 more | 2020-03-31 |
| 10599433 | Cache management operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Abhijeet Ashok Chachad +1 more | 2020-03-24 |
| 10162641 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca +3 more | 2018-12-25 |
| 9606803 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca +3 more | 2017-03-28 |
| 9489307 | Multi domain bridge with auto snoop response | Timothy David Anderson | 2016-11-08 |
| 9465741 | Multi processor multi domain conversion bridge with out of order return buffering | Kai Chirca, Matthew D. Pierson, Timothy David Anderson | 2016-10-11 |
| 9465742 | Synchronizing barrier support with zero performance impact | Kai Chirca | 2016-10-11 |
| 9465767 | Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect | Kai Chirca, Matthew D. Pierson, Timothy David Anderson | 2016-10-11 |
| 9372808 | Deadlock-avoiding coherent system on chip interconnect | Matthew D. Pierson, Kai Chirca | 2016-06-21 |
| 9372799 | Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion | Matthew D. Pierson, Kai Chirca, Timothy David Anderson | 2016-06-21 |
| 9304954 | Multi processor bridge with mixed Endian mode support | Matthew D. Pierson, Kai Chirca | 2016-04-05 |
| 9208120 | Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect | Kai Chirca, Matthew D. Pierson, Timothy David Anderson | 2015-12-08 |
| 9152586 | Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion | Matthew D. Pierson, Kai Chirca, Timothy David Anderson | 2015-10-06 |
| 6829739 | Apparatus and method for data buffering | — | 2004-12-07 |