Issued Patents All Time
Showing 25 most recent of 119 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430201 | Multi-processor bridge with cache allocate awareness | Daniel Wu, Matthew D. Pierson | 2025-09-30 |
| 12423481 | Secure master and secure guest endpoint security firewall | Timothy David Anderson, Joseph Zbiciak, Matthew D. Pierson | 2025-09-23 |
| 12386696 | Delayed snoop for improved multi-process false sharing parallel thread performance | Timothy David Anderson | 2025-08-12 |
| 12379929 | Branch prediction using loop iteration count | Paul Daniel Gauvreau, David E. Smith | 2025-08-05 |
| 12373515 | Computational primitives using a matrix multiplication accelerator | Arthur John Redfern, Timothy David Anderson, Chenchi Luo, Zhenhua Yu | 2025-07-29 |
| 12360844 | Credit aware central arbitration for multi-endpoint, multi-core system | Matthew D. Pierson, Daniel Wu | 2025-07-15 |
| 12360843 | Multicore shared cache operation engine | Timothy David Anderson, Joseph Zbiciak, David E. Smith, Matthew D. Pierson | 2025-07-15 |
| 12333284 | Nested loop control | Timothy David Anderson, Todd T. Hahn, Alan L. Davis | 2025-06-17 |
| 12321282 | Slot/sub-slot prefetch architecture for multiple memory requestors | Joseph Zbiciak, Matthew D. Pierson | 2025-06-03 |
| 12314187 | Software-hardware memory management modes | Timothy David Anderson, Joseph Zbiciak, Daniel Wu | 2025-05-27 |
| 12223165 | Multicore, multibank, fully concurrent coherence controller | Matthew D. Pierson, Timothy David Anderson | 2025-02-11 |
| 12197332 | Memory pipeline control in a hierarchical memory system | Abhijeet Ashok Chachad, Timothy David Anderson, David Matthew Thompson | 2025-01-14 |
| 12197917 | Exit history based branch prediction | Timothy David Anderson, David E. Smith, Paul Daniel Gauvreau | 2025-01-14 |
| 12182398 | Virtual network pre-arbitration for deadlock avoidance and enhanced performance | Matthew D. Pierson, Daniel Wu | 2024-12-31 |
| 12175244 | Nested loop control | Timothy David Anderson, Todd T. Hahn, Alan L. Davis | 2024-12-24 |
| 12159030 | Multicore shared cache operation engine | Matthew D. Pierson, David E. Smith, Timothy David Anderson | 2024-12-03 |
| 12141435 | Configurable cache for coherent system | Matthew D. Pierson | 2024-11-12 |
| 12135646 | Cache coherence shared state suppression | Abhijeet Ashok Chachad, David Matthew Thompson, Timothy David Anderson | 2024-11-05 |
| 12099400 | Streaming engine with deferred exception reporting | Joseph Zbiciak, Timothy David Anderson, Duc Quang Bui | 2024-09-24 |
| 12072824 | Multicore bus architecture with non-blocking high performance transaction credit system | David Matthew Thompson, Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Matthew D. Pierson | 2024-08-27 |
| 12072812 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Naveen Bhoria +3 more | 2024-08-27 |
| 12050914 | Cache management operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Daniel Wu, Abhijeet Ashok Chachad +1 more | 2024-07-30 |
| 11972236 | Nested loop control | Timothy David Anderson, Todd T. Hahn, Alan L. Davis | 2024-04-30 |
| 11960567 | Implementing fundamental computational primitives using a matrix multiplication accelerator (MMA) | Arthur John Redfern, Timothy David Anderson, Chenchi Luo, Zhenhua Yu | 2024-04-16 |
| 11940918 | Memory pipeline control in a hierarchical memory system | Abhijeet Ashok Chachad, Timothy David Anderson, David Matthew Thompson | 2024-03-26 |