Issued Patents All Time
Showing 51–75 of 119 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11341052 | Multi-processor, multi-domain, multi-protocol, cache coherent, speculation aware shared memory and interconnect | Matthew D. Pierson, Timothy David Anderson, Joseph Zbiciak | 2022-05-24 |
| 11321268 | Multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels | David Matthew Thompson, Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Matthew D. Pierson | 2022-05-03 |
| 11307858 | Cache preload operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Daniel Wu, Abhijeet Ashok Chachad +1 more | 2022-04-19 |
| 11307988 | Configurable cache for multi-endpoint heterogeneous coherent system | Matthew D. Pierson | 2022-04-19 |
| 11294681 | Processing device with a microbranch target buffer for branch prediction using loop iteration count | Paul Daniel Gauvreau, David E. Smith | 2022-04-05 |
| 11269774 | Delayed snoop for improved multi-process false sharing parallel thread performance | Timothy David Anderson | 2022-03-08 |
| 11243883 | Cache coherence shared state suppression | Abhijeet Ashok Chachad, David Matthew Thompson, Timothy David Anderson | 2022-02-08 |
| 11237968 | Multicore shared cache operation engine | Matthew D. Pierson, David E. Smith, Timothy David Anderson | 2022-02-01 |
| 11212256 | Flexible hybrid firewall architecture | Amritpal Singh Mundra, Brian J. Karguth, Timothy David Anderson, Charles Fuoco | 2021-12-28 |
| 11138117 | Memory pipeline control in a hierarchical memory system | Abhijeet Ashok Chachad, Timothy David Anderson, David Matthew Thompson | 2021-10-05 |
| 11119776 | Cache management operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Daniel Wu, Abhijeet Ashok Chachad +1 more | 2021-09-14 |
| 11106463 | System and method for addressing data in memory | Timothy David Anderson, Duc Quang Bui, Joseph Zbiciak | 2021-08-31 |
| 11099993 | Multi-processor bridge with cache allocate awareness | Daniel Wu, Matthew D. Pierson | 2021-08-24 |
| 11099994 | Virtual network pre-arbitration for deadlock avoidance and enhanced performance | Matthew D. Pierson, Daniel Wu | 2021-08-24 |
| 11086778 | Multicore shared cache operation engine | Timothy David Anderson, Joseph Zbiciak, David E. Smith, Matthew D. Pierson | 2021-08-10 |
| 11086967 | Implementing fundamental computational primitives using a matrix multiplication accelerator (MMA) | Arthur John Redfern, Timothy David Anderson, Chenchi Luo, Zhenhua Yu | 2021-08-10 |
| 11074190 | Slot/sub-slot prefetch architecture for multiple memory requestors | Joseph Zbiciak, Matthew D. Pierson | 2021-07-27 |
| 11055095 | Nested loop control | Timothy David Anderson, Todd T. Hahn, Alan L. Davis | 2021-07-06 |
| 11036648 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Naveen Bhoria +3 more | 2021-06-15 |
| 10990529 | Multi-power-domain bridge with prefetch and write merging | Daniel Wu, Matthew D. Pierson | 2021-04-27 |
| 10990398 | Mechanism for interrupting and resuming execution on an unprotected pipeline processor | Timothy David Anderson, Joseph Zbiciak | 2021-04-27 |
| 10963255 | Implied fence on stream open | Naveen Bhoria, Timothy David Anderson, Duc Quang Bui, Abhijeet Ashok Chachad, Son Hung Tran | 2021-03-30 |
| 10817587 | Reconfigurable matrix multiplier system and method | Arthur John Redfern, Donald E. Steiss, Timothy David Anderson | 2020-10-27 |
| 10802974 | Virtual network pre-arbitration for deadlock avoidance and enhanced performance | Matthew D. Pierson, Daniel Wu | 2020-10-13 |
| 10795844 | Multicore bus architecture with non-blocking high performance transaction credit system | David Matthew Thompson, Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Matthew D. Pierson | 2020-10-06 |