Issued Patents All Time
Showing 25 most recent of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430201 | Multi-processor bridge with cache allocate awareness | Kai Chirca, Daniel Wu | 2025-09-30 |
| 12423481 | Secure master and secure guest endpoint security firewall | Timothy David Anderson, Joseph Zbiciak, Kai Chirca | 2025-09-23 |
| 12360843 | Multicore shared cache operation engine | Kai Chirca, Timothy David Anderson, Joseph Zbiciak, David E. Smith | 2025-07-15 |
| 12360844 | Credit aware central arbitration for multi-endpoint, multi-core system | Kai Chirca, Daniel Wu | 2025-07-15 |
| 12321282 | Slot/sub-slot prefetch architecture for multiple memory requestors | Kai Chirca, Joseph Zbiciak | 2025-06-03 |
| 12223165 | Multicore, multibank, fully concurrent coherence controller | Kai Chirca, Timothy David Anderson | 2025-02-11 |
| 12182398 | Virtual network pre-arbitration for deadlock avoidance and enhanced performance | Daniel Wu, Kai Chirca | 2024-12-31 |
| 12159030 | Multicore shared cache operation engine | Kai Chirca, David E. Smith, Timothy David Anderson | 2024-12-03 |
| 12141435 | Configurable cache for coherent system | Kai Chirca | 2024-11-12 |
| 12079470 | Streaming engine with fetch ahead hysteresis | — | 2024-09-03 |
| 12072812 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca +3 more | 2024-08-27 |
| 12072824 | Multicore bus architecture with non-blocking high performance transaction credit system | David Matthew Thompson, Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca | 2024-08-27 |
| 11907528 | Multi-processor bridge with cache allocate awareness | Kai Chirca, Daniel Wu | 2024-02-20 |
| 11803505 | Multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels | David Matthew Thompson, Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca | 2023-10-31 |
| 11789872 | Slot/sub-slot prefetch architecture for multiple memory requestors | Kai Chirca, Joseph Zbiciak | 2023-10-17 |
| 11755203 | Multicore shared cache operation engine | Kai Chirca, David E. Smith, Timothy David Anderson | 2023-09-12 |
| 11720248 | Configurable cache for multi-endpoint heterogeneous coherent system | Kai Chirca | 2023-08-08 |
| 11687238 | Virtual network pre-arbitration for deadlock avoidance and enhanced performance | Daniel Wu, Kai Chirca | 2023-06-27 |
| 11501024 | Secure master and secure guest endpoint security firewall | Timothy David Anderson, Joseph Zbiciak, Kai Chirca | 2022-11-15 |
| 11429526 | Credit aware central arbitration for multi-endpoint, multi-core system | Kai Chirca, Daniel Wu | 2022-08-30 |
| 11422938 | Multicore, multibank, fully concurrent coherence controller | Kai Chirca, Timothy David Anderson | 2022-08-23 |
| 11347644 | Distributed error detection and correction with hamming code handoff | Kai Chirca, Daniel Wu | 2022-05-31 |
| 11341052 | Multi-processor, multi-domain, multi-protocol, cache coherent, speculation aware shared memory and interconnect | Kai Chirca, Timothy David Anderson, Joseph Zbiciak | 2022-05-24 |
| 11321268 | Multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels | David Matthew Thompson, Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca | 2022-05-03 |
| 11307988 | Configurable cache for multi-endpoint heterogeneous coherent system | Kai Chirca | 2022-04-19 |