Issued Patents All Time
Showing 26–50 of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11237968 | Multicore shared cache operation engine | Kai Chirca, David E. Smith, Timothy David Anderson | 2022-02-01 |
| 11099994 | Virtual network pre-arbitration for deadlock avoidance and enhanced performance | Daniel Wu, Kai Chirca | 2021-08-24 |
| 11099993 | Multi-processor bridge with cache allocate awareness | Kai Chirca, Daniel Wu | 2021-08-24 |
| 11086778 | Multicore shared cache operation engine | Kai Chirca, Timothy David Anderson, Joseph Zbiciak, David E. Smith | 2021-08-10 |
| 11074190 | Slot/sub-slot prefetch architecture for multiple memory requestors | Kai Chirca, Joseph Zbiciak | 2021-07-27 |
| 11068164 | Streaming engine with fetch ahead hysteresis | — | 2021-07-20 |
| 11036648 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca +3 more | 2021-06-15 |
| 10990529 | Multi-power-domain bridge with prefetch and write merging | Daniel Wu, Kai Chirca | 2021-04-27 |
| 10802974 | Virtual network pre-arbitration for deadlock avoidance and enhanced performance | Daniel Wu, Kai Chirca | 2020-10-13 |
| 10795844 | Multicore bus architecture with non-blocking high performance transaction credit system | David Matthew Thompson, Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca | 2020-10-06 |
| 10642490 | Streaming engine with fetch ahead hysteresis | — | 2020-05-05 |
| 10394718 | Slot/sub-slot prefetch architecture for multiple memory requestors | Kai Chirca, Joseph Zbiciak | 2019-08-27 |
| 10311007 | Multicore bus architecture with non-blocking high performance transaction credit system | David Matthew Thompson, Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca | 2019-06-04 |
| 10209887 | Streaming engine with fetch ahead hysteresis | — | 2019-02-19 |
| 10162641 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca +3 more | 2018-12-25 |
| 10037439 | Secure master and secure guest endpoint security firewall | Timothy David Anderson, Joseph Zbiciak, Kai Chirca | 2018-07-31 |
| 9904645 | Multicore bus architecture with non-blocking high performance transaction credit system | David Matthew Thompson, Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca | 2018-02-27 |
| 9898415 | Slot/sub-slot prefetch architecture for multiple memory requestors | Kai Chirca, Joseph Zbiciak | 2018-02-20 |
| 9652404 | Multicore, multibank, fully concurrent coherence controller | Kai Chirca | 2017-05-16 |
| 9606803 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca +3 more | 2017-03-28 |
| 9489314 | Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC | Kai Chirca, Timothy David Anderson | 2016-11-08 |
| 9465767 | Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect | Kai Chirca, Daniel Wu, Timothy David Anderson | 2016-10-11 |
| 9465741 | Multi processor multi domain conversion bridge with out of order return buffering | Kai Chirca, Daniel Wu, Timothy David Anderson | 2016-10-11 |
| 9424193 | Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems | Kai Chirca | 2016-08-23 |
| 9372796 | Optimum cache access scheme for multi endpoint atomic access in a multicore system | Kai Chirca | 2016-06-21 |