Issued Patents All Time
Showing 51–64 of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9372799 | Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion | Daniel Wu, Kai Chirca, Timothy David Anderson | 2016-06-21 |
| 9372808 | Deadlock-avoiding coherent system on chip interconnect | Daniel Wu, Kai Chirca | 2016-06-21 |
| 9304954 | Multi processor bridge with mixed Endian mode support | Daniel Wu, Kai Chirca | 2016-04-05 |
| 9304925 | Distributed data return buffer for coherence system with speculative address support | Kai Chirca | 2016-04-05 |
| 9298665 | Multicore, multibank, fully concurrent coherence controller | Kai Chirca | 2016-03-29 |
| 9239798 | Prefetcher with arbitrary downstream prefetch cancelation | Joseph Zbiciak, Kai Chirca, Amitabh Menon, Timothy David Anderson | 2016-01-19 |
| 9213656 | Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems | Kai Chirca | 2015-12-15 |
| 9208120 | Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect | Kai Chirca, Daniel Wu, Timothy David Anderson | 2015-12-08 |
| 9152586 | Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion | Daniel Wu, Kai Chirca, Timothy David Anderson | 2015-10-06 |
| 9129071 | Coherence controller slot architecture allowing zero latency write commit | Kai Chirca, Timothy David Anderson | 2015-09-08 |
| 9075928 | Hazard detection and elimination for coherent endpoint allowing out-of-order execution | Kai Chirca | 2015-07-07 |
| 9009414 | Prefetch address hit prediction to reduce memory access latency | Timothy David Anderson, Joseph Zbiciak | 2015-04-14 |
| 8977819 | Prefetch stream filter with FIFO allocation and stream direction prediction | Kai Chirca, Joseph Zbiciak, Timothy David Anderson | 2015-03-10 |
| 8788759 | Double-buffered data storage to reduce prefetch generation stalls | Joseph Zbiciak | 2014-07-22 |