| 11366783 |
Multi-headed multi-buffer for buffering data for processing |
Raghu Prabhakar, Nathan Francis Sheeley, Sitanshu Gupta, Sumti Jairath, Matheen Musaddiq |
2022-06-21 |
| 9465753 |
Memory management unit that applies rules based on privilege identifier |
Joseph Zbiciak |
2016-10-11 |
| 9239798 |
Prefetcher with arbitrary downstream prefetch cancelation |
Matthew D. Pierson, Joseph Zbiciak, Kai Chirca, Timothy David Anderson |
2016-01-19 |
| 9110845 |
Memory management unit that applies rules based on privilege identifier |
Joseph Zbiciak |
2015-08-18 |
| 8806110 |
Flexible memory protection and translation unit |
Joseph Zbiciak, Timothy David Anderson |
2014-08-12 |
| 8732370 |
Multilayer arbitration for access to multiple destinations |
Kai Chirca, Timothy David Anderson |
2014-05-20 |
| 8732551 |
Memory controller with automatic error detection and correction |
Kai Chirca, Timothy David Anderson |
2014-05-20 |
| 8683114 |
Device security features supporting a distributed shared memory system |
Joseph Zbiciak |
2014-03-25 |
| 7725687 |
Register file bypass with optional results storage and separate predication register file in a VLIW processor |
David Hoyle |
2010-05-25 |
| 7673120 |
Inter-cluster communication network and heirarchical register files for clustered VLIW processors |
David Hoyle |
2010-03-02 |
| 7269707 |
Multiple patches to on-chip ROM in a processor with a multilevel memory system without affecting performance |
Subash Chandar Govindarajan, Venkatesh Natarajan, Vijay Sindagi |
2007-09-11 |
| 6983297 |
Shifting an operand left or right while minimizing the number of multiplexor stages |
Ajit Deepak Gupte |
2006-01-03 |
| 6981130 |
Forwarding the results of operations to dependent instructions more quickly via multiplexers working in parallel |
Ajit Deepak Gupte |
2005-12-27 |
| 6647511 |
Reconfigurable datapath for processor debug functions |
Gary L. Swoboda, Madathil R. Karthikeyan, David R. Matt |
2003-11-11 |