Issued Patents All Time
Showing 26–50 of 119 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11907528 | Multi-processor bridge with cache allocate awareness | Daniel Wu, Matthew D. Pierson | 2024-02-20 |
| 11875155 | Processing device with a microbranch target buffer for branch prediction using loop iteration count | Paul Daniel Gauvreau, David E. Smith | 2024-01-16 |
| 11853225 | Software-hardware memory management modes | Timothy David Anderson, Joseph Zbiciak, Daniel Wu | 2023-12-26 |
| 11836494 | System and method for addressing data in memory | Timothy David Anderson, Duc Quang Bui, Joseph Zbiciak | 2023-12-05 |
| 11822786 | Delayed snoop for improved multi-process false sharing parallel thread performance | Timothy David Anderson | 2023-11-21 |
| 11816485 | Nested loop control | Timothy David Anderson, Todd T. Hahn, Alan L. Davis | 2023-11-14 |
| 11803505 | Multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels | David Matthew Thompson, Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Matthew D. Pierson | 2023-10-31 |
| 11789872 | Slot/sub-slot prefetch architecture for multiple memory requestors | Joseph Zbiciak, Matthew D. Pierson | 2023-10-17 |
| 11782718 | Implied fence on stream open | Naveen Bhoria, Timothy David Anderson, Duc Quang Bui, Abhijeet Ashok Chachad, Son Hung Tran | 2023-10-10 |
| 11755203 | Multicore shared cache operation engine | Matthew D. Pierson, David E. Smith, Timothy David Anderson | 2023-09-12 |
| 11720248 | Configurable cache for multi-endpoint heterogeneous coherent system | Matthew D. Pierson | 2023-08-08 |
| 11693661 | Mechanism for interrupting and resuming execution on an unprotected pipeline processor | Timothy David Anderson, Joseph Zbiciak | 2023-07-04 |
| 11687238 | Virtual network pre-arbitration for deadlock avoidance and enhanced performance | Matthew D. Pierson, Daniel Wu | 2023-06-27 |
| 11675700 | Cache coherence shared state suppression | Abhijeet Ashok Chachad, David Matthew Thompson, Timothy David Anderson | 2023-06-13 |
| 11580024 | Memory pipeline control in a hierarchical memory system | Abhijeet Ashok Chachad, Timothy David Anderson, David Matthew Thompson | 2023-02-14 |
| 11573847 | Streaming engine with deferred exception reporting | Joseph Zbiciak, Timothy David Anderson, Duc Quang Bui | 2023-02-07 |
| 11573802 | User mode event handling | — | 2023-02-07 |
| 11501024 | Secure master and secure guest endpoint security firewall | Timothy David Anderson, Joseph Zbiciak, Matthew D. Pierson | 2022-11-15 |
| 11461106 | Programmable event testing | Timothy David Anderson | 2022-10-04 |
| 11442709 | Nested loop control | Timothy David Anderson, Todd T. Hahn, Alan L. Davis | 2022-09-13 |
| 11429526 | Credit aware central arbitration for multi-endpoint, multi-core system | Matthew D. Pierson, Daniel Wu | 2022-08-30 |
| 11422938 | Multicore, multibank, fully concurrent coherence controller | Matthew D. Pierson, Timothy David Anderson | 2022-08-23 |
| 11403110 | Storing a result of a first instruction of an execute packet in a holding register prior to completion of a second instruction of the execute packet | Timothy David Anderson, Paul Daniel Gauvreau | 2022-08-02 |
| 11372646 | Exit history based branch prediction | Timothy David Anderson, David E. Smith, Paul Daniel Gauvreau | 2022-06-28 |
| 11347644 | Distributed error detection and correction with hamming code handoff | Daniel Wu, Matthew D. Pierson | 2022-05-31 |