Issued Patents All Time
Showing 25 most recent of 103 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417186 | Write merging on stores with different tags | Timothy David Anderson, Pete Michael Hippleheuser | 2025-09-16 |
| 12393521 | Methods and apparatus to facilitate write miss caching in cache system | Timothy David Anderson, Pete Michael Hippleheuser | 2025-08-19 |
| 12380035 | Methods and apparatus to facilitate read-modify-write support in a coherent victim cache with parallel data paths | Timothy David Anderson, Pete Michael Hippleheuser | 2025-08-05 |
| 12332790 | Multi-level cache security | Abhijeet Ashok Chachad, David Matthew Thompson | 2025-06-17 |
| 12321284 | Methods and apparatus to facilitate atomic operations in victim cache | Timothy David Anderson, Pete Michael Hippleheuser | 2025-06-03 |
| 12321749 | Look up table with data element promotion | Duc Quang Bui, Dheera Balasubramanian, Sahithi KRISHNA | 2025-06-03 |
| 12321270 | Hardware coherence for memory controller | Abhijeet Ashok Chachad, David Matthew Thompson | 2025-06-03 |
| 12321285 | Victim cache with write miss merging | Timothy David Anderson, Pete Michael Hippleheuser | 2025-06-03 |
| 12314720 | Look-up table write | Duc Quang Bui, Dheera Balasubramanian Samudrala | 2025-05-27 |
| 12292839 | Write merging on stores with different privilege levels | Timothy David Anderson, Pete Michael Hippleheuser | 2025-05-06 |
| 12271314 | Cache size change | Abhijeet Ashok Chachad, David Matthew Thompson, Neelima Muralidharan | 2025-04-08 |
| 12265477 | Hybrid victim cache and write miss buffer with fence operation | Timothy David Anderson, Pete Michael Hippleheuser | 2025-04-01 |
| 12259826 | Methods and apparatus for multi-banked victim cache with dual datapath | Timothy David Anderson, Pete Michael Hippleheuser | 2025-03-25 |
| 12242852 | Look-up table initialize | Dheera Balasubramanian Samudrala, Duc Quang Bui, Rama Venkatasubramanian | 2025-03-04 |
| 12216591 | Atomic compare and swap in a coherent cache system | Timothy David Anderson, Pete Michael Hippleheuser | 2025-02-04 |
| 12210463 | Aggressive write flush scheme for a victim cache | Timothy David Anderson, Pete Michael Hippleheuser | 2025-01-28 |
| 12197331 | Hardware coherence signaling protocol | Abhijeet Ashok Chachad, David Matthew Thompson, Pete Michael Hippleheuser | 2025-01-14 |
| 12197347 | Methods and apparatus to reduce bank pressure using aggressive write merging | Timothy David Anderson, Pete Michael Hippleheuser | 2025-01-14 |
| 12189540 | Fully pipelined read-modify-write support | Timothy David Anderson, Pete Michael Hippleheuser | 2025-01-07 |
| 12182038 | Methods and apparatus for allocation in a victim cache system | Timothy David Anderson, Pete Michael Hippleheuser | 2024-12-31 |
| 12147353 | Methods and apparatus for read-modify-write support in multi-banked data RAM cache for bank arbitration | Timothy David Anderson, Pete Michael Hippleheuser | 2024-11-19 |
| 12141078 | Victim cache with dynamic allocation of entries | Timothy David Anderson, Pete Michael Hippleheuser | 2024-11-12 |
| 12141073 | Methods and apparatus for inflight data forwarding and invalidation of pending writes in store queue | Timothy David Anderson, Pete Michael Hippleheuser | 2024-11-12 |
| 12141601 | Global coherence operations | Abhijeet Ashok Chachad, David Matthew Thompson, Neelima Muralidharan | 2024-11-12 |
| 12141079 | Atomic operations and histogram operations in a cache pipeline | Timothy David Anderson, Pete Michael Hippleheuser | 2024-11-12 |