Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12341534 | Butterfly network on load data return | Joseph Zbiciak, Duc Quang Bui, Timothy David Anderson | 2025-06-24 |
| 12321749 | Look up table with data element promotion | Duc Quang Bui, Naveen Bhoria, Sahithi KRISHNA | 2025-06-03 |
| 11809362 | Superimposing butterfly network controls for pattern combinations | Joseph Zbiciak, Sureshkumar Govindaraj | 2023-11-07 |
| 11804858 | Butterfly network on load data return | Joseph Zbiciak, Duc Quang Bui, Timothy David Anderson | 2023-10-31 |
| 11221982 | Superimposing butterfly network controls for pattern combinations | Joseph Zbiciak, Sureshkumar Govindaraj | 2022-01-11 |
| 11101825 | Butterfly network on load data return | Joseph Zbiciak, Due Quang Bui, Timothy David Anderson | 2021-08-24 |
| 10761850 | Look up table with data element promotion | Duc Quang Bui, Naveen Bhoria, Sahithi KRISHNA | 2020-09-01 |
| 10530397 | Butterfly network on load data return | Joseph Zbiciak, Duc Quang Bui, Timothy David Anderson | 2020-01-07 |
| 10387354 | Superimposing butterfly network controls for pattern combinations | Joseph Zbiciak, Sureshkumar Govindaraj | 2019-08-20 |
| 10140239 | Superimposing butterfly network controls for pattern combinations | Joseph Zbiciak, Sureshkumar Govindaraj | 2018-11-27 |
| 9195610 | Transaction info bypass for nodes coupled to an interconnect fabric | Raguram Damodaran | 2015-11-24 |
| 9075743 | Managing bandwidth allocation in a processing node using distributed arbitration | Raguram Damodaran, Abhijeet Ashok Chachad, Roger Kyle Castille, David Quintin Bell | 2015-07-07 |
| 8732416 | Requester based transaction status reporting in a system with multi-level memory | Raguram Damodaran, Abhijeet Ashok Chachad, Ramakrishnan Venkatasubramanian, Naveen Bhoria | 2014-05-20 |
| 8683115 | Programmable mapping of external requestors to privilege classes for access protection | Joseph Zbiciak | 2014-03-25 |
| 8607000 | Efficient cache allocation by optimizing size and order of allocate commands based on bytes required by CPU | Abhijeet Ashok Chachad, Roger Kyle Castille, Joseph Zbiciak | 2013-12-10 |
| 8560896 | Priority based exception mechanism for multi-level cache controller | Joseph Zbiciak, Raguram Damodaran, Abhijeet Ashok Chachad | 2013-10-15 |