Issued Patents All Time
Showing 25 most recent of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11709679 | Providing load address predictions using address prediction tables based on load path history in processor-based systems | Rami Mohammad Al Sheikh | 2023-07-25 |
| 11537532 | Lookahead priority collection to support priority elevation | Abhijeet Ashok Chachad, Ramakrishnan Venkatasubramanian, Joseph Zbiciak | 2022-12-27 |
| 10713180 | Lookahead priority collection to support priority elevation | Abhijeet Ashok Chachad, Ramakrishnan Venkatasubramanian, Joseph Zbiciak | 2020-07-14 |
| 10635446 | Reconfiguring execution pipelines of out-of-order (OOO) computer processors based on phase training and prediction | Shivam Priyadarshi, Anil Krishna | 2020-04-28 |
| 10551896 | Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase | Shivam Priyadarshi, Anil Krishna, Jeffrey Todd Bridges, Ryan D. Wells, Norman S. Gargash +1 more | 2020-02-04 |
| 10474462 | Dynamic pipeline throttling using confidence-based weighting of in-flight branch instructions | Shivam Priyadarshi, Rami Mohammad Al Sheikh, Michael Scott McIlvaine, Jeffrey Todd Bridges | 2019-11-12 |
| 10223118 | Providing references to previously decoded instructions of recently-provided instructions to be executed by a processor | Vignyan Reddy Kothinti Naresh, Shivam Priyadarshi | 2019-03-05 |
| 10203745 | Apparatus and method for dynamic power reduction in a unified scheduler | Milind Ram Kulkarni, Rami Mohammad Al Sheikh | 2019-02-12 |
| 10108417 | Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor | Anil Krishna, Rodney Wayne Smith, Sandeep Suresh Navada, Shivam Priyadarshi | 2018-10-23 |
| 10089114 | Multiple instruction issuance with parallel inter-group and intra-group picking | Milind Ram Kulkarni, Rami Mohammad Al Sheikh | 2018-10-02 |
| 9965395 | Memory attribute sharing between differing cache levels of multilevel cache | Joseph Zbiciak, Naveen Bhoria | 2018-05-08 |
| 9851774 | Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase | Shivam Priyadarshi, Anil Krishna, Jeffrey Todd Bridges, Ryan D. Wells, Norman S. Gargash +1 more | 2017-12-26 |
| 9830152 | Selective storing of previously decoded instructions of frequently-called instruction sequences in an instruction sequence buffer to be executed by a processor | Vignyan Reddy Kothinti Naresh, Shivam Priyadarshi | 2017-11-28 |
| 9582285 | Speculative history forwarding in overriding branch predictors, and related circuits, methods, and computer-readable media | Rami Mohammad Al Sheikh | 2017-02-28 |
| 9575901 | Programmable address-based write-through cache control | Abhijeet Ashok Chachad, Naveen Bhoria, David Matthew Thompson | 2017-02-21 |
| RE46193 | Distributed power control for controlling power consumption based on detected activity of logic blocks | Timothy David Anderson, Lewis Nardini, Jose Luis Flores, Abhijeet Ashok Chachad, Joseph Zbiciak +1 more | 2016-11-01 |
| 9390011 | Zero cycle clock invalidate operation | Naveen Bhoria, Abhijeet Ashok Chachad | 2016-07-12 |
| 9298643 | Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty | Jonathan (Son) Hung Tran, Abhijeet Ashok Chachad, Joseph Zbiciak | 2016-03-29 |
| 9268708 | Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence | Abhijeet Ashok Chachad, Jonathan (Son) Hung Tran, David Matthew Thompson | 2016-02-23 |
| 9244837 | Zero cycle clock invalidate operation | Naveen Bhoria, Abhijeet Ashok Chachad | 2016-01-26 |
| 9195610 | Transaction info bypass for nodes coupled to an interconnect fabric | Dheera Balasubramanian | 2015-11-24 |
| 9189331 | Programmable address-based write-through cache control | Abhijeet Ashok Chachad, Naveen Bhoria | 2015-11-17 |
| 9183084 | Memory attribute sharing between differing cache levels of multilevel cache | Joseph Zbiciak, Naveen Bhoria | 2015-11-10 |
| 9075744 | Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty | Jonathan (Son) Hung Tran, Abhijeet Ashok Chachad, Joseph Zbiciak | 2015-07-07 |
| 9075743 | Managing bandwidth allocation in a processing node using distributed arbitration | Abhijeet Ashok Chachad, Dheera Balasubramanian, Roger Kyle Castille, David Quintin Bell | 2015-07-07 |