Issued Patents All Time
Showing 25 most recent of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411692 | Storage of prediction-related data | Houdhaifa BOUZGUARROU, Alexander Cole Shulyak | 2025-09-09 |
| 12411771 | Combiner cache structure | Houdhaifa BOUZGUARROU, Guillaume Bolbenes | 2025-09-09 |
| 12405797 | Branch prediction circuitry | — | 2025-09-02 |
| 12405800 | Branch prediction based on a predicted confidence that a corresponding function of sampled register state correlates to a later branch instruction outcome | Houdhaifa BOUZGUARROU | 2025-09-02 |
| 12373218 | Technique for predicting behaviour of control flow instructions | Houdhaifa BOUZGUARROU, Alexander Cole Shulyak | 2025-07-29 |
| 12260220 | Accelerating fetch target queue (FTQ) processing in a processor | Saransh JAIN, Daren Eugene Streett, Michael Scott McIlvaine, Somasundaram Arunachalam | 2025-03-25 |
| 12229568 | Methods and circuitry for efficient management of local branch history registers | Ahmed Abulila, Daren Eugene Streett, Michael Scott McIlvaine | 2025-02-18 |
| 11995443 | Reuse of branch information queue entries for multiple instances of predicted control instructions in captured loops in a processor | Daren Eugene Streett | 2024-05-28 |
| 11928474 | Selectively updating branch predictors for loops executed from loop buffers in a processor | Saransh JAIN, Michael Scott McIlvaine, Daren Eugene Streett | 2024-03-12 |
| 11915002 | Providing extended branch target buffer (BTB) entries for storing trunk branch metadata and leaf branch metadata | Saransh JAIN, Daren Eugene Streett, Michael Scott McIlvaine | 2024-02-27 |
| 11789740 | Performing branch predictor training using probabilistic counter updates in a processor | Michael Scott McIlvaine, Daren Eugene Streett | 2023-10-17 |
| 11768688 | Methods and circuitry for efficient management of local branch history registers | Ahmed Abulila, Daren Eugene Streett, Michael Scott McIlvaine | 2023-09-26 |
| 11726787 | Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetching | Michael Scott McIlvaine | 2023-08-15 |
| 11709679 | Providing load address predictions using address prediction tables based on load path history in processor-based systems | Raguram Damodaran | 2023-07-25 |
| 11698789 | Restoring speculative history used for making speculative predictions for instructions processed in a processor employing control independence techniques | Vignyan Reddy Kothinti Naresh, Shivam Priyadarshi, Arthur Perais | 2023-07-11 |
| 11487545 | Processor branch prediction circuit employing back-invalidation of prediction cache entries based on decoded branch instructions and related methods | Daren Eugene Streett, Michael Scott McIlvaine, Richard W. Doing, Robert Douglas Clancy | 2022-11-01 |
| 11392387 | Predicting load-based control independent (CI) register data independent (DI) (CIRDI) instructions as CI memory data dependent (DD) (CIMDD) instructions for replay in speculative misprediction recovery in a processor | Vignyan Reddy Kothinti Naresh, Arthur Perais, Shivam Priyadarshi | 2022-07-19 |
| 11360773 | Reusing fetched, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-fetching | Michael Scott McIlvaine | 2022-06-14 |
| 11334488 | Cache management circuits for predictive adjustment of cache control policies based on persistent, history-based cache control information | Arthur Perais, Michael Scott McIlvaine | 2022-05-17 |
| 11327763 | Opportunistic consumer instruction steering based on producer instruction value prediction in a multi-cluster processor | Arthur Perais, Shivam Priyadarshi, Yusuf Cagatay Tekmen, Vignyan Reddy Kothinti Naresh | 2022-05-10 |
| 11243772 | Efficient load value prediction | Derek Robert Hower | 2022-02-08 |
| 11074077 | Reusing executed, flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction re-execution | Michael Scott McIlvaine | 2021-07-27 |
| 11068273 | Swapping and restoring context-specific branch predictor states on context switches in a processor | Michael Scott McIlvaine | 2021-07-20 |
| 11061824 | Deferring cache state updates in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculative | Vignyan Reddy Kothinti Naresh, Arthur Perais, Shivam Priyadarshi | 2021-07-13 |
| 11036512 | Systems and methods for processing instructions having wide immediate operands | Arthur Perais, Rodney Wayne Smith, Shivam Priyadarshi, Vignyan Reddy Kothinti Naresh | 2021-06-15 |