| 11755330 |
Tracking exact convergence to guide the recovery process in response to a mispredicted branch |
Shivam Priyadarshi |
2023-09-12 |
| 11698789 |
Restoring speculative history used for making speculative predictions for instructions processed in a processor employing control independence techniques |
Rami Mohammad Al Sheikh, Shivam Priyadarshi, Arthur Perais |
2023-07-11 |
| 11620133 |
Reduction of data cache access in a processing system |
— |
2023-04-04 |
| 11494191 |
Tracking exact convergence to guide the recovery process in response to a mispredicted branch |
Shivam Priyadarshi |
2022-11-08 |
| 11392410 |
Operand pool instruction reservation clustering in a scheduler circuit in a processor |
Shivam Priyadarshi, Yusuf Cagatay Tekmen, Rodney Wayne Smith |
2022-07-19 |
| 11392387 |
Predicting load-based control independent (CI) register data independent (DI) (CIRDI) instructions as CI memory data dependent (DD) (CIMDD) instructions for replay in speculative misprediction recovery in a processor |
Arthur Perais, Rami Mohammad Al Sheikh, Shivam Priyadarshi |
2022-07-19 |
| 11327763 |
Opportunistic consumer instruction steering based on producer instruction value prediction in a multi-cluster processor |
Arthur Perais, Shivam Priyadarshi, Yusuf Cagatay Tekmen, Rami Mohammad Al Sheikh |
2022-05-10 |
| 11269642 |
Dynamic hammock branch training for branch hammock detection in an instruction stream executing in a processor |
— |
2022-03-08 |
| 11068272 |
Tracking and communication of direct/indirect source dependencies of producer instructions executed in a processor to source dependent consumer instructions to facilitate processor optimizations |
— |
2021-07-20 |
| 11061677 |
Recovering register mapping state of a flushed instruction employing a snapshot of another register mapping state and traversing reorder buffer (ROB) entries in a processor |
Kiran Ravi Seth, Yusuf Cagatay Tekmen, Rodney Wayne Smith, Shivam Priyadarshi |
2021-07-13 |
| 11061824 |
Deferring cache state updates in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculative |
Arthur Perais, Rami Mohammad Al Sheikh, Shivam Priyadarshi |
2021-07-13 |
| 11061683 |
Limiting replay of load-based control independent (CI) instructions in speculative misprediction recovery in a processor |
Shivam Priyadarshi |
2021-07-13 |
| 11036512 |
Systems and methods for processing instructions having wide immediate operands |
Arthur Perais, Rodney Wayne Smith, Shivam Priyadarshi, Rami Mohammad Al Sheikh |
2021-06-15 |
| 10929139 |
Providing predictive instruction dispatch throttling to prevent resource overflows in out-of-order processor (OOP)-based devices |
Lisa R. Hsu, Gregory M. Wright |
2021-02-23 |
| 10896041 |
Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devices |
Shivam Priyadarshi, Arthur Perais, Yusuf Cagatay Tekmen, Rami Mohammad Al Sheikh, Rodney Wayne Smith |
2021-01-19 |
| 10877768 |
Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processor |
Shivam Priyadarshi, Yusuf Cagatay Tekmen, Kiran Ravi Seth, Rodney Wayne Smith |
2020-12-29 |
| 10783011 |
Deadlock free resource management in block based computing architectures |
Gregory M. Wright |
2020-09-22 |
| 10725782 |
Providing variable interpretation of usefulness indicators for memory tables in processor-based systems |
Anil Krishna, Yongseok Yi, Eric Rotenberg, Gregory M. Wright |
2020-07-28 |
| 10437592 |
Reduced logic level operation folding of context history in a history register in a prediction system for a processor-based system |
Anil Krishna, Yongseok Yi |
2019-10-08 |
| 10255074 |
Selective flushing of instructions in an instruction pipeline in a processor back to an execution-resolved target address, in response to a precise interrupt |
Rami Mohammad Al Sheikh, Harold W. Cain, III |
2019-04-09 |
| 9830152 |
Selective storing of previously decoded instructions of frequently-called instruction sequences in an instruction sequence buffer to be executed by a processor |
Shivam Priyadarshi, Raguram Damodaran |
2017-11-28 |
