Issued Patents All Time
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11755330 | Tracking exact convergence to guide the recovery process in response to a mispredicted branch | Vignyan Reddy Kothinti Naresh | 2023-09-12 |
| 11698789 | Restoring speculative history used for making speculative predictions for instructions processed in a processor employing control independence techniques | Vignyan Reddy Kothinti Naresh, Rami Mohammad Al Sheikh, Arthur Perais | 2023-07-11 |
| 11669333 | Method, apparatus, and system for reducing live readiness calculations in reservation stations | Rodney Wayne Smith, Raghavan MADHAVAN, Luke Yen, Yusuf Cagatay Tekmen | 2023-06-06 |
| 11494191 | Tracking exact convergence to guide the recovery process in response to a mispredicted branch | Vignyan Reddy Kothinti Naresh | 2022-11-08 |
| 11392387 | Predicting load-based control independent (CI) register data independent (DI) (CIRDI) instructions as CI memory data dependent (DD) (CIMDD) instructions for replay in speculative misprediction recovery in a processor | Vignyan Reddy Kothinti Naresh, Arthur Perais, Rami Mohammad Al Sheikh | 2022-07-19 |
| 11392410 | Operand pool instruction reservation clustering in a scheduler circuit in a processor | Yusuf Cagatay Tekmen, Rodney Wayne Smith, Vignyan Reddy Kothinti Naresh | 2022-07-19 |
| 11327763 | Opportunistic consumer instruction steering based on producer instruction value prediction in a multi-cluster processor | Arthur Perais, Yusuf Cagatay Tekmen, Rami Mohammad Al Sheikh, Vignyan Reddy Kothinti Naresh | 2022-05-10 |
| 11113068 | Performing flush recovery using parallel walks of sliced reorder buffers (SROBs) | Yusuf Cagatay Tekmen, Rodney Wayne Smith, Kiran Ravi Seth | 2021-09-07 |
| 11061677 | Recovering register mapping state of a flushed instruction employing a snapshot of another register mapping state and traversing reorder buffer (ROB) entries in a processor | Kiran Ravi Seth, Yusuf Cagatay Tekmen, Rodney Wayne Smith, Vignyan Reddy Kothinti Naresh | 2021-07-13 |
| 11061683 | Limiting replay of load-based control independent (CI) instructions in speculative misprediction recovery in a processor | Vignyan Reddy Kothinti Naresh | 2021-07-13 |
| 11061824 | Deferring cache state updates in a non-speculative cache memory in a processor-based system in response to a speculative data request until the speculative data request becomes non-speculative | Vignyan Reddy Kothinti Naresh, Arthur Perais, Rami Mohammad Al Sheikh | 2021-07-13 |
| 11036512 | Systems and methods for processing instructions having wide immediate operands | Arthur Perais, Rodney Wayne Smith, Rami Mohammad Al Sheikh, Vignyan Reddy Kothinti Naresh | 2021-06-15 |
| 11023243 | Latency-based instruction reservation station clustering in a scheduler circuit in a processor | Yusuf Cagatay Tekmen, Rodney Wayne Smith | 2021-06-01 |
| 10896041 | Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devices | Arthur Perais, Vignyan Reddy Kothinti Naresh, Yusuf Cagatay Tekmen, Rami Mohammad Al Sheikh, Rodney Wayne Smith | 2021-01-19 |
| 10877768 | Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processor | Yusuf Cagatay Tekmen, Kiran Ravi Seth, Rodney Wayne Smith, Vignyan Reddy Kothinti Naresh | 2020-12-29 |
| 10860328 | Providing late physical register allocation and early physical register release in out-of-order processor (OOP)-based devices implementing a checkpoint-based architecture | Rodney Wayne Smith, Yusuf Cagatay Tekmen, Luke Yen | 2020-12-08 |
| 10831254 | Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements | SeyedMajid Zahedi, Derek Robert Hower, Carl A. Waldspurger, Jeffrey Todd Bridges, Sanjay Patel +4 more | 2020-11-10 |
| 10635446 | Reconfiguring execution pipelines of out-of-order (OOO) computer processors based on phase training and prediction | Anil Krishna, Raguram Damodaran | 2020-04-28 |
| 10551896 | Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase | Anil Krishna, Raguram Damodaran, Jeffrey Todd Bridges, Ryan D. Wells, Norman S. Gargash +1 more | 2020-02-04 |
| 10474462 | Dynamic pipeline throttling using confidence-based weighting of in-flight branch instructions | Rami Mohammad Al Sheikh, Raguram Damodaran, Michael Scott McIlvaine, Jeffrey Todd Bridges | 2019-11-12 |
| 10379863 | Slice construction for pre-executing data dependent loads | Rami Mohammad Al Sheikh, Brandon H. Dwiel, Derek Robert Hower | 2019-08-13 |
| 10303608 | Intelligent data prefetching using address delta prediction | Rami Mohammad Al Sheikh, Brandon H. Dwiel, David John Palframan, Derek Robert Hower, Muntaquim Chowdhury | 2019-05-28 |
| 10223118 | Providing references to previously decoded instructions of recently-provided instructions to be executed by a processor | Vignyan Reddy Kothinti Naresh, Raguram Damodaran | 2019-03-05 |
| 10223278 | Selective bypassing of allocation in a cache | Brandon H. Dwiel, Rami Mohammad Al Sheikh, Harold W. Cain, III | 2019-03-05 |
| 10185668 | Cost-aware cache replacement | Rami Mohammad Al Sheikh, Harold W. Cain, III | 2019-01-22 |