Issued Patents All Time
Showing 1–25 of 112 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11586462 | Memory access request for a memory protocol | Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Timothy J. Slegel | 2023-02-21 |
| 11567771 | Method and apparatus for back end gather/scatter memory coalescing | Nagesh Bangalore Lakshminarayana, Daniel Jonathan Ernst, Sanyam Mehta | 2023-01-31 |
| 11567767 | Method and apparatus for front end gather/scatter memory coalescing | Rabin Sugumar, Nagesh Bangalore Lakshminarayana, Daniel Jonathan Ernst, Sanyam Mehta | 2023-01-31 |
| 11550723 | Method, apparatus, and system for memory bandwidth aware data prefetching | Niket K. Choudhary, David Scott Ray, Thomas Philip Speier, Eric F. Robinson, Nikhil Narendradev Sharma +3 more | 2023-01-10 |
| 11442864 | Managing prefetch requests based on stream information for previously recognized streams | Utkarsh Mathur | 2022-09-13 |
| 11275614 | Dynamic update of the number of architected registers assigned to software threads using spill counts | Hubertus Franke, Charles Ray Johns, Hung Q. Le, Ravi Nair, James Allan Kahle | 2022-03-15 |
| 11221971 | QoS-class based servicing of requests for a shared resource | Derek Robert Hower, Carl A. Waldspurger | 2022-01-11 |
| 11182198 | Indicator-based prioritization of transactions | Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Timothy Siegel | 2021-11-23 |
| 10963387 | Methods of cache preloading on a partition or a context switch | Vijayalakshmi Srinivasan, Jason D. Zebchuk | 2021-03-30 |
| 10885015 | Database system transaction management | Donna N. Dillenberger, Michel H. T. Hack, Hong Min, Gong Su, James Zu-Chia Teng | 2021-01-05 |
| 10831254 | Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements | Shivam Priyadarshi, SeyedMajid Zahedi, Derek Robert Hower, Carl A. Waldspurger, Jeffrey Todd Bridges +4 more | 2020-11-10 |
| 10831537 | Dynamic update of the number of architected registers assigned to software threads using spill counts | Hubertus Franke, Charles Ray Johns, Hung Q. Le, Ravi Nair | 2020-11-10 |
| 10802971 | Cache memory transaction shielding via prefetch suppression | Pratap C. Pattnaik | 2020-10-13 |
| 10740106 | Determining if transactions that are about to run out of resources can be salvaged or need to be aborted | Fadi Y. Busaba, Michael K. Gschwind, Maged M. Michael, Valentina Salapura | 2020-08-11 |
| 10565003 | Hint instruction for managing transactional aborts in transactional memory computing environments | Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura +2 more | 2020-02-18 |
| 10521262 | Memory access request for a memory protocol | Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Timothy J. Slegel | 2019-12-31 |
| 10353734 | Prioritization of transactions based on execution by transactional core with super core indicator | Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel | 2019-07-16 |
| 10268588 | Methods of cache preloading on a partition or a context switch | Vijayalakshmi Srinivasan, Jason D. Zebchuk | 2019-04-23 |
| 10255074 | Selective flushing of instructions in an instruction pipeline in a processor back to an execution-resolved target address, in response to a precise interrupt | Vignyan Reddy Kothinti Naresh, Rami Mohammad Al Sheikh | 2019-04-09 |
| 10223278 | Selective bypassing of allocation in a cache | Shivam Priyadarshi, Brandon H. Dwiel, Rami Mohammad Al Sheikh | 2019-03-05 |
| 10223154 | Hint instruction for managing transactional aborts in transactional memory computing environments | Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura +2 more | 2019-03-05 |
| 10210019 | Hint instruction for managing transactional aborts in transactional memory computing environments | Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura +2 more | 2019-02-19 |
| 10185668 | Cost-aware cache replacement | Rami Mohammad Al Sheikh, Shivam Priyadarshi | 2019-01-22 |
| 10169240 | Reducing memory access bandwidth based on prediction of memory request size | Brandon H. Dwiel, Shivam Priyadarshi | 2019-01-01 |
| 10120802 | Transactional memory coherence control | Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel | 2018-11-06 |