Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11487547 | Extended asynchronous data mover functions compatibility indication | Louis P. Gomes, Bruce C. Giamei, Mark S. Farrell, Matthias Klein | 2022-11-01 |
| 11314555 | Synchronous re-execution of a data transformation operation to obtain further details regarding an exception | Matthias Klein, Anthony T. Sofia, Simon Weishaupt, Bruce C. Giamei, Louis P. Gomes +1 more | 2022-04-26 |
| 11226839 | Maintaining compatibility for complex functions over multiple machine generations | Matthias Klein, Bruce C. Giamei, Anthony T. Sofia, Mark S. Farrell, Scott Barnett Swaney | 2022-01-18 |
| 11221850 | Sort and merge instruction for a general-purpose processor | Bruce C. Giamei, Martin Recktenwald, Donald W. Schmidt, Aditya N. Puranik, Mark S. Farrell +3 more | 2022-01-11 |
| 11182198 | Indicator-based prioritization of transactions | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz | 2021-11-23 |
| 11150905 | Efficiency for coordinated start interpretive execution exit for a multithreaded processor | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +4 more | 2021-10-19 |
| 11151267 | Move data and set storage key based on key function control | Elpida Tzortzatos | 2021-10-19 |
| 10985778 | Verifying the correctness of a deflate compression accelerator | Mark S. Farrell, Bruce C. Giamei, Matthias Klein, Ashutosh Misra, Simon Weishaupt +1 more | 2021-04-20 |
| 10949212 | Saving and restoring machine state between multiple executions of an instruction | Bruce C. Giamei, Martin Recktenwald, Donald W. Schmidt, Aditya N. Puranik, Mark S. Farrell +3 more | 2021-03-16 |
| 10944423 | Verifying the correctness of a deflate compression accelerator | Mark S. Farrell, Bruce C. Giamei, Matthias Klein, Ashutosh Misra, Simon Weishaupt +1 more | 2021-03-09 |
| 10430188 | Next instruction access intent instruction for indicating usage of a storage operand by one or more instructions subsequent to a next sequential instruction | Christian Jacobi, Chung-Lung K. Shum, Gustav E. Sittmann, III | 2019-10-01 |
| 9996472 | Extract target cache attribute facility and instruction therefor | Dan F. Greiner | 2018-06-12 |
| 9507646 | Cycle-level thread alignment on multi-threaded processors | Ramon Bertran, Pradip Bose, Alper Buyuktosunoglu | 2016-11-29 |
| 9495306 | Dynamic management of a processor state with transient cache memory | Jonathan D. Bradbury, Dan F. Greiner, Michael K. Gschwind, Christian Jacobi, Younes Manton +3 more | 2016-11-15 |
| 9454377 | Speculative branch handling for transaction abort | Michael Billeci, James J. Bonanno, Adam B. Collura, Christian Jacobi, Anthony Saporito | 2016-09-27 |
| 9280480 | Extract target cache attribute facility and instruction therefor | Dan F. Greiner | 2016-03-08 |
| 9244856 | Dynamic address translation with translation table entry format control for identifying format of the translation table entry | Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Charles F. Webb | 2016-01-26 |
| 8631216 | Dynamic address translation with change record override | Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Charles F. Webb | 2014-01-14 |
| 7281115 | Method, system and program product for clearing selected storage translation buffer entries | Lisa C. Heller, Erwin Pfeffer, Kenneth E. Plambeck | 2007-10-09 |
| 7020761 | Blocking processing restrictions based on page indices | Bruce Wagar, Ute Gaertner, Lisa C. Heller, Erwin Pfeffer | 2006-03-28 |