Issued Patents All Time
Showing 1–25 of 264 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11934220 | Clock comparator sign control | Eberhard Engler, Michel H. T. Hack, Timothy J. Slegel, Joachim von Buttlar | 2024-03-19 |
| 11809870 | Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor | Damian L. Osisek, Timothy J. Slegel, Lisa C. Heller | 2023-11-07 |
| 11199870 | Clock comparator sign control | Eberhard Engler, Michel H. T. Hack, Timothy J. Slegel, Joachim von Buttlar | 2021-12-14 |
| 11188326 | Function virtualization facility for function query of a processor | Damian L. Osisek, Timothy J. Slegel | 2021-11-30 |
| 11150905 | Efficiency for coordinated start interpretive execution exit for a multithreaded processor | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Lisa C. Heller +4 more | 2021-10-19 |
| 11086624 | Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor | Damian L. Osisek, Timothy J. Slegel, Lisa C. Heller | 2021-08-10 |
| 11080087 | Transaction begin/end instructions | Christian Jacobi, Marcel Mitran, Timothy J. Slegel | 2021-08-03 |
| 11074180 | Creating a dynamic address translation with translation exception qualifiers | Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer | 2021-07-27 |
| 11010066 | Identifying processor attributes based on detecting a guarded storage event | Christian Jacobi, Marcel Mitran, Volodymyr Paprotski, Anthony Saporito, Timothy J. Slegel | 2021-05-18 |
| 10977190 | Dynamic address translation with access control in an emulator environment | Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel +1 more | 2021-04-13 |
| 10963391 | Extract target cache attribute facility and instruction therefor | Timothy J. Slegel | 2021-03-30 |
| 10956156 | Conditional transaction end instruction | Christian Jacobi, Marcel Mitran, Donald W. Schmidt, Timothy J. Slegel | 2021-03-23 |
| 10929130 | Guarded storage event handling during transactional execution | Christian Jacobi, Volodymyr Paprotski, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel | 2021-02-23 |
| 10915325 | Parsing-enhancement facility | John R. Ehrman | 2021-02-09 |
| 10908903 | Efficiency for coordinated start interpretive execution exit for a multithreaded processor | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Lisa C. Heller +4 more | 2021-02-02 |
| 10901736 | Conditional instruction end operation | Christian Jacobi, Marcel Mitran, Donald W. Schmidt, Timothy J. Slegel | 2021-01-26 |
| 10846090 | Instruction for performing a pseudorandom number generate operation | Bernd Nerz, Tamas Visegrady | 2020-11-24 |
| 10831476 | Compare and delay instructions | Charles W. Gainey, Jr., Christian Jacobi, Marcel Mitran, Donald W. Schmidt, Timothy J. Slegel | 2020-11-10 |
| 10831479 | Instruction to move data in a right-to-left direction | Timothy J. Slegel, John R. Ehrman, Anthony Saporito, Aaron Tsai | 2020-11-10 |
| 10776112 | Performing an operation absent host intervention | Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Gustav E. Sittmann, III | 2020-09-15 |
| 10732858 | Loading and storing controls regulating the operation of a guarded storage facility | Christian Jacobi, Marcel Mitran, Volodymyr Paprotski, Anthony Saporito, Timothy J. Slegel | 2020-08-04 |
| 10725685 | Load logical and shift guarded instruction | Christian Jacobi, Marcel Mitran, Volodymyr Paprotski, Anthony Saporito, Timothy J. Slegel | 2020-07-28 |
| 10719415 | Randomized testing within transactional execution | Christian Jacobi, Timothy J. Slegel | 2020-07-21 |
| 10713048 | Conditional branch to an indirectly specified location | Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel | 2020-07-14 |
| 10684863 | Restricted instructions in transactional execution | Christian Jacobi, Timothy J. Slegel | 2020-06-16 |