Issued Patents All Time
Showing 1–25 of 358 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12204832 | Logical clock connection in an integrated circuit design | Ali S. El-Zein, Viresh Paruthi, Alvan W. Ng, Benedikt Geukes, Klaus-Dieter Schubert +6 more | 2025-01-21 |
| 12188979 | Error protection analysis of an integrated circuit | Benjamin Neil Trombley, Karl Evan Smock Anderson, Bodo Hoppe, Erica Stuecheli, Shiri Moran +3 more | 2025-01-07 |
| 11907724 | In-memory trace with overlapping processing and logout | Lior Binyamini, Ludmila Zernakov, Markus Kaltenbach, Jang-Soo Lee | 2024-02-20 |
| 11907124 | Using a shadow copy of a cache in a cache hierarchy | Yair Fried, Aaron Tsai, Eyal Naor, Christian Jacobi, Timothy C. Bronson | 2024-02-20 |
| 11892949 | Reducing cache transfer overhead in a system | Christian Zoellin, Christian Jacobi, Martin Recktenwald, Anthony Saporito, Aaron Tsai | 2024-02-06 |
| 11817697 | Method to limit the time a semiconductor device operates above a maximum operating voltage | Adam B. Collura, Michael Romain, William V. Huott, Pawel Owczarczyk, Christian Jacobi +9 more | 2023-11-14 |
| 11586542 | Reducing cache transfer overhead in a system | Christian Zoellin, Christian Jacobi, Martin Recktenwald, Anthony Saporito, Aaron Tsai | 2023-02-21 |
| 11366759 | Temporarily suppressing processing of a restrained storage operand request | Bruce C. Giamei, Christian Jacobi, Daniel V. Rosa, Anthony Saporito, Donald W. Schmidt | 2022-06-21 |
| 11347513 | Suppressing branch prediction updates until forward progress is made in execution of a previously aborted transaction | Michael K. Gschwind, Valentina Salapura | 2022-05-31 |
| 11243770 | Latent modification instruction for substituting functionality of instructions during transactional execution | Michael K. Gschwind, Valentina Salapura, Timothy J. Slegel | 2022-02-08 |
| 11163574 | Method for maintaining a branch prediction history table | Wolfgang Gellerich, Peter M. Held, Martin Schwidefsky | 2021-11-02 |
| 11113055 | Store instruction to store instruction dependency | Edward T. Malley, Jang-Soo Lee, Anthony Saporito, Gregory W. Alexander | 2021-09-07 |
| 11080052 | Determining the effectiveness of prefetch instructions | Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Timothy J. Slegel | 2021-08-03 |
| 11061684 | Architecturally paired spill/reload multiple instructions for suppressing a snapshot latest value determination | Michael K. Gschwind, Timothy J. Slegel | 2021-07-13 |
| 11048635 | Controlling a rate of prefetching based on bus bandwidth | Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi | 2021-06-29 |
| 11010298 | Reducing cache transfer overhead in a system | Christian Zoellin, Christian Jacobi, Martin Recktenwald, Anthony Saporito, Aaron Tsai | 2021-05-18 |
| 11010276 | Configurable code fingerprint | Giles R. Frazier, Michael K. Gschwind, Christian Jacobi | 2021-05-18 |
| 11010192 | Register restoration using recovery buffers | Michael K. Gschwind, Timothy J. Slegel | 2021-05-18 |
| 11010168 | Effectiveness and prioritization of prefetches | Michael K. Gschwind, Christian Jacobi, Anthony Saporito | 2021-05-18 |
| 11010160 | Load register on condition immediate instruction | Wolfgang Gellerich, Martin Schwidefsky, Kai Weber | 2021-05-18 |
| 11003452 | Effectiveness and prioritization of prefetches | Michael K. Gschwind, Christian Jacobi, Anthony Saporito | 2021-05-11 |
| 10996982 | Regulating hardware speculative processing around a transaction | Fadi Y. Busaba, Michael K. Gschwind, Eric M. Schwarz | 2021-05-04 |
| 10956337 | Temporarily suppressing processing of a restrained storage operand request | Bruce C. Giamei, Christian Jacobi, Daniel V. Rosa, Anthony Saporito, Donald W. Schmidt | 2021-03-23 |
| 10936314 | Suppressing branch prediction on a repeated execution of an aborted transaction | Michael K. Gschwind, Valentina Salapura | 2021-03-02 |
| 10929297 | Prefetch protocol for transactional memory | Michael K. Gschwind, Valentina Salapura | 2021-02-23 |