CS

Chung-Lung K. Shum

IBM: 354 patents #49 of 70,183Top 1%
Globalfoundries: 3 patents #1,029 of 4,424Top 25%
IS International Business Systems: 1 patents #1 of 22Top 5%
📍 Wappingers Falls, NY: #1 of 884 inventorsTop 1%
🗺 New York: #42 of 115,490 inventorsTop 1%
Overall (All Time): #840 of 4,157,543Top 1%
358
Patents All Time

Issued Patents All Time

Showing 51–75 of 358 patents

Patent #TitleCo-InventorsDate
10565117 Instruction to cancel outstanding cache prefetches Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz 2020-02-18
10558560 Prefetch insensitive transactional memory Michael K. Gschwind, Valentina Salapura, Timothy J. Slegel 2020-02-11
10558552 Configurable code fingerprint Giles R. Frazier, Michael K. Gschwind, Christian Jacobi 2020-02-11
10552164 Sharing snapshots between restoration and recovery Michael K. Gschwind, Valentina Salapura, Timothy J. Slegel 2020-02-04
10534713 Deferred response to a prefetch request Michael K. Gschwind, Valentina Salapura 2020-01-14
10521350 Determining the effectiveness of prefetch instructions Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Timothy J. Slegel 2019-12-31
10521351 Temporarily suppressing processing of a restrained storage operand request Bruce C. Giamei, Christian Jacobi, Daniel V. Rosa, Anthony Saporito, Donald W. Schmidt 2019-12-31
10496292 Saving/restoring guarded storage controls in a virtualized environment Dan F. Greiner, Christian Jacobi, Damian L. Osisek, Anthony Saporito, Timothy J. Slegel 2019-12-03
10496311 Run-time instrumentation of guarded storage event processing Dan F. Greiner, Christian Jacobi, Anthony Saporito, Timothy J. Slegel 2019-12-03
10489209 Management of resources within a computing environment Fadi Y. Busaba, Steven R. Carlough, Christopher A. Krygowski, Brian R. Prasky 2019-11-26
10489382 Register restoration invalidation based on a context switch Michael K. Gschwind, Valentina Salapura, Timothy J. Slegel 2019-11-26
10474576 Prefetch protocol for transactional memory Michael K. Gschwind, Valentina Salapura 2019-11-12
10474577 Prefetch protocol for transactional memory Michael K. Gschwind, Valentina Salapura 2019-11-12
10452395 Instruction to query cache residency Dan F. Greiner, Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Timothy J. Slegel 2019-10-22
10430194 Method for maintaining a branch prediction history table Wolfgang Gellerich, Peter M. Held, Martin Schwidefsky 2019-10-01
10430188 Next instruction access intent instruction for indicating usage of a storage operand by one or more instructions subsequent to a next sequential instruction Christian Jacobi, Timothy Siegel, Gustav E. Sittmann, III 2019-10-01
10423418 Method for maintaining a branch prediction history table Wolfgang Gellerich, Peter M. Held, Martin Schwidefsky 2019-09-24
10417126 Non-coherent read in a strongly consistent cache system for frequently read but rarely updated data Jane H. Bartik, Nicholas C. Matsakis, Craig R. Walters 2019-09-17
10379862 Effectiveness and prioritization of prefeteches Michael K. Gschwind, Christian Jacobi, Anthony Saporito 2019-08-13
10372457 Effectiveness and prioritization of prefetches Michael K. Gschwind, Christian Jacobi, Anthony Saporito 2019-08-06
10372611 Deferred response to a prefetch request Michael K. Gschwind, Valentina Salapura 2019-08-06
10365927 Non-default instruction handling within transaction Jonathan D. Bradbury, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz, Valentina Salapura 2019-07-30
10346305 Interprocessor memory status communication Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel 2019-07-09
10346197 Inducing transactional aborts in other processing threads Fadi Y. Busaba, Valentina Salapura 2019-07-09
10339049 Garbage collection facility grouping infrequently accessed data units in designated transient memory area Giles R. Frazier, Michael K. Gschwind, Christian Jacobi, Younes Manton, Anthony Saporito 2019-07-02