Issued Patents All Time
Showing 101–125 of 358 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10157131 | Transactional execution processor having a co-processor accelerator, both sharing a higher level cache | Fadi Y. Busaba, Michael K. Gschwind, Eric M. Schwarz | 2018-12-18 |
| 10157119 | Configurable code fingerprint | Giles R. Frazier, Michael K. Gschwind, Christian Jacobi | 2018-12-18 |
| 10152419 | Deferred response to a prefetch request | Michael K. Gschwind, Valentina Salapura | 2018-12-11 |
| 10152418 | Speculation control for improving transaction success rate, and instruction therefor | Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel | 2018-12-11 |
| 10146692 | Deferred response to a prefetch request | Michael K. Gschwind, Valentina Salapura | 2018-12-04 |
| 10120804 | Hybrid tracking of transaction read and write sets | Michael K. Gschwind, Valentina Salapura | 2018-11-06 |
| 10114752 | Detecting cache conflicts by utilizing logical address comparisons in a transactional memory | Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel | 2018-10-30 |
| 10083076 | Salvaging lock elision transactions with instructions to change execution type | Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Valentina Salapura | 2018-09-25 |
| 10061703 | Prefetch insensitive transactional memory | Michael K. Gschwind, Valentina Salapura, Timothy J. Slegel | 2018-08-28 |
| 10061586 | Latent modification instruction for transactional execution | Michael K. Gschwind, Valentina Salapura, Timothy J. Slegel | 2018-08-28 |
| 10055348 | Transactional execution in a multi-processor environment that monitors memory conflicts in a shared cache | Fadi Y. Busaba, Michael K. Gschwind, Eric M. Schwarz | 2018-08-21 |
| 10055230 | Accurate tracking of transactional read and write sets with speculation | Michael K. Gschwind, Valentina Salapura | 2018-08-21 |
| 10042749 | Prefetch insensitive transactional memory | Michael K. Gschwind, Valentina Salapura, Timothy J. Slegel | 2018-08-07 |
| 10025715 | Conditional inclusion of data in a transactional memory read set | Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel | 2018-07-17 |
| 10025592 | Selectively blocking branch prediction for a predetermined number of instructions | James J. Bonanno, Ulrich Mayer, Anthony Saporito, Timothy J. Slegel | 2018-07-17 |
| 10019265 | Selectively blocking branch prediction for a predetermined number of instructions | James J. Bonanno, Ulrich Mayer, Anthony Saporito, Timothy J. Slegel | 2018-07-10 |
| 10013351 | Transactional execution processor having a co-processor accelerator, both sharing a higher level cache | Fadi Y. Busaba, Michael K. Gschwind, Eric M. Schwarz | 2018-07-03 |
| 9983904 | Multithreaded transactions | Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz | 2018-05-29 |
| 9971690 | Transactional memory operations with write-only atomicity | Michael K. Gschwind, Timothy J. Slegel | 2018-05-15 |
| 9971629 | Dynamic releasing of cache lines | Jonathan D. Bradbury, Michael K. Gschwind, Timothy J. Slegel | 2018-05-15 |
| 9952976 | Allowing non-cacheable loads within a transaction | Jonathan D. Bradbury, Michael K. Gschwind, Valentina Salapura | 2018-04-24 |
| 9952804 | Hardware transaction transient conflict resolution | Jonathan D. Bradbury, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2018-04-24 |
| 9946521 | Programmable code fingerprint | Giles R. Frazier, Michael K. Gschwind, Christian Jacobi | 2018-04-17 |
| 9946494 | Hardware transaction transient conflict resolution | Jonathan D. Bradbury, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2018-04-17 |
| 9940135 | Instruction stream modification for memory transaction protection | Fadi Y. Busaba, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Timothy J. Slegel | 2018-04-10 |