Issued Patents All Time
Showing 25 most recent of 836 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11972259 | Instructions to count a number of contiguous register elements having specific values in a selected location | Markus Kaltenbach, Jentje Leenstra, Brett Olsson | 2024-04-30 |
| 11972260 | Instructions to count a number of contiguous register elements having specific values in a selected location | Markus Kaltenbach, Jentje Leenstra, Brett Olsson | 2024-04-30 |
| 11586462 | Memory access request for a memory protocol | Fadi Y. Busaba, Harold W. Cain, III, Valentina Salapura, Timothy J. Slegel | 2023-02-21 |
| 11579806 | Portions of configuration state registers in-memory | Valentina Salapura | 2023-02-14 |
| 11347513 | Suppressing branch prediction updates until forward progress is made in execution of a previously aborted transaction | Valentina Salapura, Chung-Lung K. Shum | 2022-05-31 |
| 11314511 | Concurrent prediction of branch addresses and update of register contents | Valentina Salapura | 2022-04-26 |
| 11287981 | Automatic pinning of units of memory | Valentina Salapura | 2022-03-29 |
| 11243770 | Latent modification instruction for substituting functionality of instructions during transactional execution | Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2022-02-08 |
| 11194580 | Selective suppression of instruction translation lookaside buffer (ITLB) access | Valentina Salapura | 2021-12-07 |
| 11182198 | Indicator-based prioritization of transactions | Fadi Y. Busaba, Harold W. Cain, III, Valentina Salapura, Eric M. Schwarz, Timothy Siegel | 2021-11-23 |
| 11150908 | Dynamic fusion of derived value creation and prediction of derived values in a subroutine branch sequence | Valentina Salapura | 2021-10-19 |
| 11150904 | Concurrent prediction of branch addresses and update of register contents | Valentina Salapura | 2021-10-19 |
| 11144320 | Selective suppression of instruction cache-related directory access | Valentina Salapura | 2021-10-12 |
| 11138127 | Initializing a data structure for use in predicting table of contents pointer values | Valentina Salapura | 2021-10-05 |
| 11138113 | Set table of contents (TOC) register instruction | Valentina Salapura | 2021-10-05 |
| 11132290 | Locality domain-based memory pools for virtualized computing environment | — | 2021-09-28 |
| 11119785 | Delaying branch prediction updates specified by a suspend branch prediction instruction until after a transaction is completed | Valentina Salapura | 2021-09-14 |
| 11119942 | Facilitating access to memory locality domain information | Jonathan D. Bradbury | 2021-09-14 |
| 11106490 | Context switch by changing memory pointers | Valentina Salapura | 2021-08-31 |
| 11099782 | Portions of configuration state registers in-memory | Valentina Salapura | 2021-08-24 |
| 11093145 | Protecting in-memory configuration state registers | Valentina Salapura | 2021-08-17 |
| 11080052 | Determining the effectiveness of prefetch instructions | Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel | 2021-08-03 |
| 11061575 | Read-only table of contents register | Valentina Salapura | 2021-07-13 |
| 11061576 | Read-only table of contents register | Valentina Salapura | 2021-07-13 |
| 11061684 | Architecturally paired spill/reload multiple instructions for suppressing a snapshot latest value determination | Chung-Lung K. Shum, Timothy J. Slegel | 2021-07-13 |