Issued Patents All Time
Showing 25 most recent of 66 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11977486 | Shadow pointer directory in an inclusive hierarchical cache | Ashraf ElSharif, Richard Joseph Branciforte, Gregory W. Alexander, Deanna Postles Dunn Berger, Timothy C. Bronson +4 more | 2024-05-07 |
| 11972260 | Instructions to count a number of contiguous register elements having specific values in a selected location | Michael K. Gschwind, Jentje Leenstra, Brett Olsson | 2024-04-30 |
| 11972259 | Instructions to count a number of contiguous register elements having specific values in a selected location | Michael K. Gschwind, Jentje Leenstra, Brett Olsson | 2024-04-30 |
| 11907724 | In-memory trace with overlapping processing and logout | Lior Binyamini, Chung-Lung K. Shum, Ludmila Zernakov, Jang-Soo Lee | 2024-02-20 |
| 11775444 | Fetch request arbiter | Willm Hinrichs, Simon H. Friedmann, Joerg Deutschle, Thomas Koehler | 2023-10-03 |
| 11748266 | Special tracking pool enhancement for core local cache address invalidates | Deanna Postles Dunn Berger, Gregory W. Alexander, Richard Joseph Branciforte, Aaron Tsai | 2023-09-05 |
| 11372776 | Method and apparatus for an efficient TLB lookup | Michael Johannes Jaspers, Girish G. Kurup, Ulrich Mayer | 2022-06-28 |
| 11182293 | Operating different processor cache levels | Simon H. Friedmann, Christian Jacobi, Ulrich Mayer, Anthony Saporito | 2021-11-23 |
| 11169922 | Method and arrangement for saving cache power | Christian Jacobi, Ulrich Mayer, Johannes C. Reichart, Anthony Saporito, Siegmund Schlechter | 2021-11-09 |
| 11144323 | Independent mapping of threads | Sam Gat-Shang Chu, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen +1 more | 2021-10-12 |
| 10997079 | Method and arrangement for saving cache power | Christian Jacobi, Ulrich Mayer, Johannes C. Reichart, Anthony Saporito, Siegmund Schlechter | 2021-05-04 |
| 10970214 | Selective downstream cache processing for data access | Willm Hinrichs, Eyal Naor, Martin Recktenwald | 2021-04-06 |
| 10956328 | Selective downstream cache processing for data access | Willm Hinrichs, Eyal Naor, Martin Recktenwald | 2021-03-23 |
| 10956341 | Multi-engine address translation facility | Uwe Brandt, Markus Helms, Christian Jacobi, Thomas Koehler, Frank Lehnert | 2021-03-23 |
| 10740240 | Method and arrangement for saving cache power | Christian Jacobi, Ulrich Mayer, Johannes C. Reichart, Anthony Saporito, Siegmund Schlechter | 2020-08-11 |
| 10691604 | Minimizing cache latencies using set predictors | Dwifuzi Coe, Christian Jacobi, Eyal Naor, Martin Recktenwald | 2020-06-23 |
| 10684951 | Minimizing cache latencies using set predictors | Dwifuzi Coe, Christian Jacobi, Eyal Naor, Martin Recktenwald | 2020-06-16 |
| 10649912 | Method and apparatus for an efficient TLB lookup | Michael Johannes Jaspers, Girish G. Kurup, Ulrich Mayer | 2020-05-12 |
| 10635603 | Multi-engine address translation facility | Uwe Brandt, Markus Helms, Christian Jacobi, Thomas Koehler, Frank Lehnert | 2020-04-28 |
| 10621105 | Multi-engine address translation facility | Uwe Brandt, Markus Helms, Christian Jacobi, Thomas Koehler, Frank Lehnert | 2020-04-14 |
| 10592414 | Filtering of redundantly scheduled write passes | Simon H. Friedmann, Girish G. Kurup, Ulrich Mayer, Martin Recktenwald | 2020-03-17 |
| 10585797 | Operating different processor cache levels | Simon H. Friedmann, Christian Jacobi, Ulrich Mayer, Anthony Saporito | 2020-03-10 |
| 10572384 | Operating different processor cache levels | Simon H. Friedmann, Christian Jacobi, Ulrich Mayer, Anthony Saporito | 2020-02-25 |
| 10545762 | Independent mapping of threads | Sam Gat-Shang Chu, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen +1 more | 2020-01-28 |
| 10540293 | Method and apparatus for an efficient TLB lookup | Michael Johannes Jaspers, Girish G. Kurup, Ulrich Mayer | 2020-01-21 |