Issued Patents All Time
Showing 26–50 of 66 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10528472 | Method and arrangement for saving cache power | Christian Jacobi, Ulrich Mayer, Johannes C. Reichart, Anthony Saporito, Siegmund Schlechter | 2020-01-07 |
| 10423412 | Instructions to count contiguous register elements having a specific value in a selected location | Michael K. Gschwind, Jentje Leenstra, Brett Olsson | 2019-09-24 |
| 10417127 | Selective downstream cache processing for data access | Willm Hinrichs, Eyal Naor, Martin Recktenwald | 2019-09-17 |
| 10409724 | Selective downstream cache processing for data access | Willm Hinrichs, Eyal Naor, Martin Recktenwald | 2019-09-10 |
| 10387150 | Instructions to count contiguous register elements having a specific value in a selected location | Michael K. Gschwind, Jentje Leenstra, Brett Olsson | 2019-08-20 |
| 10380033 | Multi-engine address translation facility | Uwe Brandt, Markus Helms, Christian Jacobi, Thomas Koehler, Frank Lehnert | 2019-08-13 |
| 10380034 | Cache return order optimization | Ulrich Mayer, Siegmund Schlechter, Maxim Scholl | 2019-08-13 |
| 10380032 | Multi-engine address translation facility | Uwe Brandt, Markus Helms, Christian Jacobi, Thomas Koehler, Frank Lehnert | 2019-08-13 |
| 10317465 | Integrated circuit chip and a method for testing the same | Wilhelm Haller, Ulrich Krauch, Nicolas Maeding, Christian Zoellin | 2019-06-11 |
| 10268582 | Operating different processor cache levels | Simon H. Friedmann, Christian Jacobi, Ulrich Mayer, Anthony Saporito | 2019-04-23 |
| 10229061 | Method and arrangement for saving cache power | Christian Jacobi, Ulrich Mayer, Johannes C. Reichart, Anthony Saporito, Siegmund Schlechter | 2019-03-12 |
| 10169234 | Translation lookaside buffer purging with concurrent cache updates | Simon H. Friedmann, Dietmar Schmunkamp, Johannes C. Reichart | 2019-01-01 |
| 10169233 | Translation lookaside buffer purging with concurrent cache updates | Simon H. Friedmann, Dietmar Schmunkamp, Johannes C. Reichart | 2019-01-01 |
| 10089231 | Filtering of redundently scheduled write passes | Simon H. Friedmann, Girish G. Kurup, Ulrich Mayer, Martin Recktenwald | 2018-10-02 |
| 10083124 | Translating virtual memory addresses to physical addresses | Uwe Brandt, Markus Helms, Christian Jacobi, Thomas Koehler, Frank Lehnert | 2018-09-25 |
| 10006965 | Integrated circuit chip and a method for testing the same | Wilhelm Haller, Ulrich Krauch, Nicolas Maeding, Christian Zoellin | 2018-06-26 |
| 9870229 | Independent mapping of threads | Sam Gat-Shang Chu, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen +1 more | 2018-01-16 |
| 9760375 | Register files for storing data operated on by instructions of multiple widths | Maarten J. Boersma, David Lang, Jentje Leenstra | 2017-09-12 |
| 9753690 | Splitable and scalable normalizer for vector data | Maarten J. Boersma, Christophe J. Layer, Silvia M. Mueller | 2017-09-05 |
| 9740486 | Register files for storing data operated on by instructions of multiple widths | Maarten J. Boersma, David Lang, Jentje Leenstra | 2017-08-22 |
| 9720696 | Independent mapping of threads | Sam Gat-Shang Chu, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen +1 more | 2017-08-01 |
| 9506986 | Integrated circuit chip and a method for testing the same | Wilhelm Haller, Ulrich Krauch, Nicolas Maeding, Christian Zoellin | 2016-11-29 |
| 9495490 | Active power dissipation detection based on erroneus clock gating equations | Christopher M. Abernathy, Maarten J. Boersma, Ulrike Schmidt | 2016-11-15 |
| 9361267 | Splitable and scalable normalizer for vector data | Maarten J. Boersma, Christophe J. Layer, Silvia M. Mueller | 2016-06-07 |
| 9361268 | Splitable and scalable normalizer for vector data | Maarten J. Boersma, Christophe J. Layer, Silvia M. Mueller | 2016-06-07 |