Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10528323 | Circuit for addition of multiple binary numbers | Manuel Beck, Ulrich Krauch, Kurt Lind, Friedrich Schroeder | 2020-01-07 |
| 10317465 | Integrated circuit chip and a method for testing the same | Markus Kaltenbach, Ulrich Krauch, Nicolas Maeding, Christian Zoellin | 2019-06-11 |
| 10168991 | Circuit for addition of multiple binary numbers | Manuel Beck, Ulrich Krauch, Kurt Lind, Friedrich Schroeder | 2019-01-01 |
| 10031995 | Detecting circuit design flaws based on timing analysis | Kurt Lind, Friedrich Schroeder, Stefan Zimmermann | 2018-07-24 |
| 10006965 | Integrated circuit chip and a method for testing the same | Markus Kaltenbach, Ulrich Krauch, Nicolas Maeding, Christian Zoellin | 2018-06-26 |
| 9506986 | Integrated circuit chip and a method for testing the same | Markus Kaltenbach, Ulrich Krauch, Nicolas Maeding, Christian Zoellin | 2016-11-29 |
| 9058456 | Method and system to fix early mode slacks in a circuit design | Ulrich Krauch, Kurt Lind, Alexander Woerner | 2015-06-16 |
| 8701059 | Method and system for repartitioning a hierarchical circuit design | Elmar Gaugler, Friedhelm Kessler | 2014-04-15 |
| 8612500 | Method and decimal arithmetic logic unit structure to generate a magnitude result of a mathematic | Ulrich Krauch, Guenter Mayer, Eric M. Schwarz | 2013-12-17 |
| 8516417 | Method and system for repartitioning a hierarchical circuit design | Elmar Gaugler, Friedhelm Kessler | 2013-08-20 |
| 8423940 | Early noise detection and noise aware routing in circuit design | Lukas Daellenbach, Elmar Gaugler, Ralf Richter | 2013-04-16 |
| 8302056 | Method and system for placement of electronic circuit components in integrated circuit design | Elmar Gaugler, Friedhelm Kessler | 2012-10-30 |
| 8286115 | Fast routing of custom macros | Holger Wetter, Maarten J. Boersma, Armin Windschiegl | 2012-10-09 |
| 8219604 | System and method for providing a double adder for decimal floating point operations | Steven R. Carlough, Wen H. Li, Eric M. Schwarz | 2012-07-10 |
| 8086657 | Adder structure with midcycle latch for power reduction | Rolf Sautter, Christoph Wandel, Ulrich Weiss | 2011-12-27 |
| 7908308 | Carry-select adder structure and method to generate orthogonal signal levels | Mark D. Mayo, Ricardo H. Nigaglioni, Hartmut Sturm | 2011-03-15 |
| 7546565 | Method for comparing two designs of electronic circuits | Joachim Fenkes, Tobias Werner, Alexander Woerner | 2009-06-09 |
| 7530038 | Method and placement tool for designing the layout of an electronic circuit | George D. Gristede, Friedhelm Kessler, Matthias Klein | 2009-05-05 |
| 7475104 | System and method for providing a double adder for decimal floating point operations | Steven R. Carlough, Wen H. Li, Eric M. Schwarz | 2009-01-06 |
| 7406495 | Adder structure with midcycle latch for power reduction | Rolf Sautter, Christoph Wandel, Ulrich Weiss | 2008-07-29 |
| 7224190 | Midcycle latch for power saving and switching reduction | Rolf Sautter, Monika Strohmer, Klaus Thumm | 2007-05-29 |
| 7095252 | Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type CMOS gates | Michael A. Haase, Rolf Sautter, Christoph Wandel | 2006-08-22 |
| 6918119 | Method and system to improve usage of an instruction window buffer in multi-processor, parallel processing environments | Jens Leenstra, Rolf Sautter, Dieter Wendel, Friedrich-Christian Wernicke | 2005-07-12 |
| 6836835 | Combined logic function for address limit checking | Harald Mielich | 2004-12-28 |
| 6292819 | Binary and decimal adder unit | Wolfgang Friedrich Bultmann, Holger Wetter, Alexander Wörner | 2001-09-18 |