Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10296691 | Optimizing the layout of circuits based on multiple design constraints | Robert L. Franch, Matthew M. Ziegler | 2019-05-21 |
| 9910949 | Synthesis tuning system for VLSI design optimization | Matthew M. Ziegler | 2018-03-06 |
| 9529951 | Synthesis tuning system for VLSI design optimization | Matthew M. Ziegler | 2016-12-27 |
| 7530038 | Method and placement tool for designing the layout of an electronic circuit | Wilhelm Haller, Friedhelm Kessler, Matthias Klein | 2009-05-05 |
| 7082595 | Schematic driven placement method and program product for custom VLSI circuit design | Yiu-Hing Chan, Jonathan Chu, Gregory A. Northrop | 2006-07-25 |
| 6219822 | Method and system for tuning of components for integrated circuits | Wei Hwang, Christophe Robert Tretz | 2001-04-17 |
| 6175949 | Method and system for selecting sizes of components for integrated circuits | Wei Hwang, Christophe Robert Tretz | 2001-01-16 |