Issued Patents All Time
Showing 25 most recent of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7284028 | Comparator eliminating need for one's complement logic for signed numbers | Kun-Lung Wu | 2007-10-16 |
| 6890766 | Dual-type thin-film field-effect transistors and applications | Thomas Doderer, Chang C. Tsuei | 2005-05-10 |
| 6620659 | Merged logic and memory combining thin film and bulk Si transistors | Philip George Emmma, Stephen M. Gates | 2003-09-16 |
| 6492227 | Method for fabricating flash memory device using dual damascene process | Li-Kong Wang, Louis L. Hsu | 2002-12-10 |
| 6437623 | Data retention registers | Louis L. Hsu, Stephen V. Kosonocky, Li-Kong Wang | 2002-08-20 |
| 6307805 | High performance semiconductor memory device with low power consumption | John E. Andersen, Terence B. Hook, Louis L. Hsu, Stephen V. Kosonocky, Li-Kong Wang | 2001-10-23 |
| 6285050 | Decoupling capacitor structure distributed above an integrated circuit and method for making same | Philip G. Emma, Stephen M. Gates | 2001-09-04 |
| 6279144 | Provably correct storage arrays | Walter Henkels, Rajiv V. Joshi, Albert Thomas Williams | 2001-08-21 |
| 6271542 | Merged logic and memory combining thin film and bulk Si transistors | Philip G. Emma, Stephen M. Gates | 2001-08-07 |
| 6230290 | Method of self programmed built in self test | David F. Heidel, Toshiaki Kirihata | 2001-05-08 |
| 6219822 | Method and system for tuning of components for integrated circuits | George D. Gristede, Christophe Robert Tretz | 2001-04-17 |
| 6175949 | Method and system for selecting sizes of components for integrated circuits | George D. Gristede, Christophe Robert Tretz | 2001-01-16 |
| 6151266 | Asynchronous multiport register file with self resetting write operation | Walter Henkels, Rajiv V. Joshi | 2000-11-21 |
| 6108798 | Self programmed built in self test | David F. Heidel, Toshiaki Kirihata | 2000-08-22 |
| 6090153 | Multi-threshold-voltage differential cascode voltage switch (DCVS) circuits | Wei Chen, Prabhakar Kudva | 2000-07-18 |
| 5995425 | Design of provably correct storage arrays | Walter Henkels, Rajiv V. Joshi, Albert Thomas Williams | 1999-11-30 |
| 5973529 | Pulse-to-static conversion latch with a self-timed control circuit | Terry I. Chappell, Walter Henkels, Rajiv V. Joshi | 1999-10-26 |
| 5939898 | Input isolation for self-resetting CMOS macros | Walter Henkels, Rajiv V. Joshi | 1999-08-17 |
| 5901304 | Emulating quasi-synchronous DRAM with asynchronous DRAM | Rajiv V. Joshi, Yasunao Katayama | 1999-05-04 |
| 5883814 | System-on-chip layout compilation | Wing K. Luk, Yasunao Katayama | 1999-03-16 |
| 5875125 | X+2X adder with multi-bit generate/propagate circuit | Xiaodong Xiao | 1999-02-23 |
| 5790839 | System integration of DRAM macros and logic cores in a single chip architecture | Wing K. Luk | 1998-08-04 |
| 5780335 | Method of forming a buried-sidewall-strap two transistor one capacitor trench cell | Walter Henkels | 1998-07-14 |
| 5777491 | High-performance differential cascode voltage switch with pass gate logic elements | Fang-Shi Jordan Lai | 1998-07-07 |
| 5617047 | Reset and pulse width control circuits for high-performance multi-port memories and register files | Walter Henkels, Rajiv V. Joshi | 1997-04-01 |