TC

Terry I. Chappell

IBM: 26 patents #4,008 of 70,183Top 6%
IN Intel: 7 patents #5,403 of 30,777Top 20%
University of California: 2 patents #4,561 of 18,278Top 25%
Overall (All Time): #95,094 of 4,157,543Top 3%
36
Patents All Time

Issued Patents All Time

Showing 25 most recent of 36 patents

Patent #TitleCo-InventorsDate
6531897 Global clock self-timed circuit with self-terminating precharge for high frequency applications Mark S. Milshtein, Milo D. Sprague, Thomas D. Fletcher 2003-03-11
6420894 Implementation of iscan cell for self-resetting dynamic circuit Xia Dai 2002-07-16
6339347 Method and apparatus for ratioed logic structure that uses zero or negative threshold voltage Kevin Dai 2002-01-15
6279024 High performance, low power incrementer for dynamic circuits Barbara A. Chappell, Sang Hoo Dhong, Mark S. Milshtein 2001-08-21
6204714 Variable width pulse generator Mark S. Milshtein, Thomas D. Fletcher, Kevin Dai, Milo D. Sprague 2001-03-20
6131182 Method and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macros Michael P. Beakes, Barbara Alana Chappell, Gary S. Ditlow, Barry Lee Dorfman, Bruce M. Fleischer +5 more 2000-10-10
6107834 Charge sharing protection for domino circuits Kevin Dai 2000-08-22
6023182 High gain pulse generator circuit with clock gating Mark S. Milshtein, Thomas D. Fletcher 2000-02-08
6005416 Compiled self-resetting CMOS logic array macros Michael P. Beakes, Barbara Alana Chappell, Gary S. Ditlow, Barry Lee Dorfman, Bruce M. Fleischer +2 more 1999-12-21
5973529 Pulse-to-static conversion latch with a self-timed control circuit Walter Henkels, Wei Hwang, Rajiv V. Joshi 1999-10-26
5942917 High speed ratioed CMOS logic structures for a pulsed input environment Barbara A. Chappell, Mark S. Milshtein, Thomas D. Fletcher 1999-08-24
5926487 High performance registers for pulsed logic Michael Kevin Ciraula, Max Eduardo De Ycaza, Sang Hoo Dhong, Rudolf A. Haring, Talal K. Jaber +3 more 1999-07-20
5920486 Parameterized cells for generating dense layouts of VLSI circuits Martin Emery Beahm, Rajiv V. Joshi 1999-07-06
5748012 Methodology to test pulsed logic circuits in pseudo-static mode Michael P. Beakes, Barbara A. Chappell, Bruce M. Fleischer, Rudolf A. Haring, Talal K. Jaber +1 more 1998-05-05
5633820 Self-resetting CMOS parallel adder with a bubble pipelined architecture, tri-rail merging logic, and enhanced testability Michael P. Beakes, Barbara Alana Chappell, Bruce M. Fleischer, Thao N. Nguyen 1997-05-27
5542067 Virtual multi-port RAM employing multiple accesses during single machine cycle Barbara A. Chappell, Mahmut K. Ebcioglu, Stanley E. Schuster 1996-07-30
5481495 Cells and read-circuits for high-performance register files Walter Henkels, Wei Hwang 1996-01-02
5471188 Fast comparator circuit Barbara A. Chappell, Bruce M. Fleischer, Stanley E. Schuster 1995-11-28
5204841 Virtual multi-port RAM Barbara A. Chappell, Mahmut K. Ebcioglu, Stanley E. Schuster 1993-04-20
5089726 Fast cycle time clocked amplifier Barbara A. Chappell, Stanley E. Schuster 1992-02-18
5015881 High speed decoding circuit with improved AND gate Barbara A. Chappell, Stanley E. Schuster 1991-05-14
4998028 High speed CMOS logic device for providing ECL compatible logic levels Barbara A. Chappell, Stanley E. Schuster 1991-03-05
4845677 Pipelined memory chip structure having improved cycle time Barbara A. Chappell, Stanley E. Schuster 1989-07-04
4843261 Complementary output, high-density CMOS decoder/driver circuit for semiconductor memories Barbara A. Chappell, Stanley E. Schuster 1989-06-27
4835419 Source-follower emitter-coupled-logic receiver circuit Barbara A. Chappell, Stanley E. Schuster 1989-05-30