| 7865747 |
Adaptive issue queue for reduced power at high performance |
Alper Buyuktosunoglu, David M. Brooks, Pradip Bose, Peter W. Cook, David Albonesi |
2011-01-04 |
$2,931,000 |
| 7821858 |
eDRAM hierarchical differential sense AMP |
Richard E. Matick |
2010-10-26 |
$4,266,000 |
| 7709299 |
Hierarchical 2T-DRAM with self-timed sensing |
Richard E. Matick |
2010-05-04 |
$4,679,000 |
| 7685457 |
Interlocked synchronous pipeline clock gating |
Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Peter W. Cook |
2010-03-23 |
$4,775,000 |
| 7499312 |
Fast, stable, SRAM cell using seven devices and hierarchical bit/sense line |
Richard E. Matick |
2009-03-03 |
$5,705,000 |
| 7475227 |
Method of stalling one or more stages in an interlocked synchronous pipeline |
Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Peter W. Cook |
2009-01-06 |
$2,860,000 |
| 7471546 |
Hierarchical six-transistor SRAM |
Richard E. Matick |
2008-12-30 |
$5,097,000 |
| 7460387 |
eDRAM hierarchical differential sense amp |
Richard E. Matick |
2008-12-02 |
$5,263,000 |
| 7460423 |
Hierarchical 2T-DRAM with self-timed sensing |
Richard E. Matick |
2008-12-02 |
$5,263,000 |
| 7308593 |
Interlocked synchronous pipeline clock gating |
Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Peter W. Cook |
2007-12-11 |
$7,826,000 |
| 7289369 |
DRAM hierarchical data path |
Richard E. Matick |
2007-10-30 |
$4,304,000 |
| 7134028 |
Processor with low overhead predictive supply voltage gating for leakage power reduction |
Pradip Bose, David M. Brooks, Peter W. Cook, Philip G. Emma, Michael K. Gschwind +1 more |
2006-11-07 |
$5,535,000 |
| 7076681 |
Processor with demand-driven clock throttling power reduction |
Pradip Bose, Daniel Citron, Peter W. Cook, Philip G. Emma, Hans M. Jacobson +3 more |
2006-07-11 |
$5,175,000 |
| 7065665 |
Interlocked synchronous pipeline clock gating |
Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Peter W. Cook |
2006-06-20 |
$5,983,000 |
| 6981096 |
Mapping and logic for combining L1 and L2 directories and/or arrays |
Richard E. Matick |
2005-12-27 |
$5,960,000 |
| 6946869 |
Method and structure for short range leakage control in pipelined circuits |
Hans M. Jacobson, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Philip G. Emma +1 more |
2005-09-20 |
$5,282,000 |
| 6925549 |
Asynchronous pipeline control interface using tag values to control passing data through successive pipeline stages |
Peter W. Cook, Andrew D. Davies, Daniel Stasiak |
2005-08-02 |
$7,293,000 |
| 6848060 |
Synchronous to asynchronous to synchronous interface |
Peter W. Cook |
2005-01-25 |
$10,247,000 |
| 6829716 |
Latch structure for interlocked pipelined CMOS (IPCMOS) circuits |
Peter W. Cook |
2004-12-07 |
$6,343,000 |
| 6608771 |
Low-power circuit structures and methods for content addressable memories and random access memories |
Hans M. Jacobson, Prabhakar Kudva, Peter W. Cook |
2003-08-19 |
$23,908,000 |
| 6512397 |
Circuit structures and methods for high-speed low-power select arbitration |
Hans M. Jacobson, Prabhakar Kudva, Peter W. Cook |
2003-01-28 |
$17,722,000 |
| 6182233 |
Interlocked pipelined CMOS |
Peter W. Cook |
2001-01-30 |
$13,187,000 |
| 6087225 |
Method for dual gate oxide dual workfunction CMOS |
Gary B. Bronner, Badih El-Kareh |
2000-07-11 |
$21,738,000 |
| 6081872 |
Cache reloading performance improvement through the use of early select techniques with and without pipelining |
Richard E. Matick |
2000-06-27 |
$38,700,000 |
| 6057188 |
Trench capacitor structures |
Badih El-Kareh, Richard L. Kleinhenz |
2000-05-02 |
$31,039,000 |
