DA

David Albonesi

UR University Of Rochester: 6 patents #56 of 1,162Top 5%
PC Prime Computer: 4 patents #6 of 116Top 6%
CU Cornell University: 2 patents #404 of 1,984Top 25%
IBM: 1 patents #44,794 of 70,183Top 65%
📍 Ithaca, NY: #86 of 1,653 inventorsTop 6%
🗺 New York: #8,460 of 115,490 inventorsTop 8%
Overall (All Time): #275,391 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Showing 1–17 of 17 patents

Patent #TitleCo-InventorsDate
10371405 Building power management systems Howard Chong, Brandon Hencey, Christine A. Shoemaker 2019-08-06
10088891 Multi-core computer processor based on a dynamic core-level power management for enhanced overall power efficiency Paula Petrica, Adam Moshe Izraelevitz, Christine A. Shoemaker 2018-10-02
8103856 Performance monitoring for new phase dynamic optimization of instruction dispatch cluster configuration Rajeev Balasubramonian, Sandhya Dwarkadas 2012-01-24
RE42213 Dynamic reconfigurable memory hierarchy Sandhya Dwarkadas, Rajeev Balasubramonian, Alper Buyuktosunoglu 2011-03-08
7865747 Adaptive issue queue for reduced power at high performance Alper Buyuktosunoglu, Stanley E. Schuster, David M. Brooks, Pradip Bose, Peter W. Cook 2011-01-04
RE41958 Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures Sandhya Dwarkadas, Rajeev Balasubramonian, Alper Buyuktosunoglu 2010-11-23
7739537 Multiple clock domain microprocessor Greg P. Semeraro, Grigorios Magklis, Michael Scott, Rajeev Balasubramonian, Sandhya Dwarkadas 2010-06-15
7571302 Dynamic data dependence tracking and its application to branch prediction Lei Chen, Steve Dropsho 2009-08-04
7490220 Multi-cluster processor operating only select number of clusters during each phase based on program statistic monitored at predetermined intervals Rajeev Balasubramonian, Sandhya Dwarkadas 2009-02-10
7089443 Multiple clock domain microprocessor Greg P. Semeraro, Grigorios Magklis, Michael Scott, Rajeev Balasubramonian, Sandhya Dwarkadas 2006-08-08
6834328 Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures Sandhya Dwarkadas, Rajeev Balasubramonian, Alper Buyuktosnoglu 2004-12-21
6684298 Dynamic reconfigurable memory hierarchy Sandhya Dwarkadas, Rajeev Balasubramonian, Alper Buyuktosnoglu 2004-01-27
6205537 Mechanism for dynamically adapting the complexity of a microprocessor 2001-03-20
5170113 Electric cable connection error-detect method and apparatus 1992-12-08
5119486 Memory board selection method and apparatus 1992-06-02
5113514 System bus for multiprocessor computer system Brian K. Langendorf, John Chang, John G. Faase, Michael J. Homberg 1992-05-12
4920539 Memory error correction system 1990-04-24