Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10620861 | Retrieve data block from determined devices | Paolo Faraboschi, Gregg B. Lesartre, Naveen Muralimanohar | 2020-04-14 |
| 10318420 | Draining a write queue based on information from a read queue | Naveen Muralimanohar | 2019-06-11 |
| 10303622 | Data write to subset of memory devices | Naveen Muralimanohar, Gregg B. Lesartre, Paolo Faraboschi, Jishen Zhao | 2019-05-28 |
| 10254988 | Memory device write based on mapping | Gregg B. Lesartre, Robert Schreiber, Jishen Zhao, Naveen Muralimanohar, Paolo Faraboschi | 2019-04-09 |
| 9846550 | Memory access methods and apparatus | Naveen Muralimanohar, Aniruddha Nagendran Udipi, Niladrish Chatterjee, Alan L. Davis, Norman Paul Jouppi | 2017-12-19 |
| 9600359 | Local error detection and global error correction | Aniruddha Nagendran Udipi, Naveen Muralimanohar, Norman Paul Jouppi, Alan L. Davis | 2017-03-21 |
| 9411757 | Memory interface | Aniruddha Nagendran Udipi, Naveen Muralimanohar, Norman Paul Jouppi, Alan L. Davis | 2016-08-09 |
| 9361955 | Memory access methods and apparatus | Naveen Muralimanohar, Aniruddha Nagendran Udipi, Niladrish Chatterjee, Alan L. Davis, Norman Paul Jouppi | 2016-06-07 |
| 8103856 | Performance monitoring for new phase dynamic optimization of instruction dispatch cluster configuration | Sandhya Dwarkadas, David Albonesi | 2012-01-24 |
| RE42213 | Dynamic reconfigurable memory hierarchy | Sandhya Dwarkadas, Alper Buyuktosunoglu, David Albonesi | 2011-03-08 |
| RE41958 | Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures | Sandhya Dwarkadas, Alper Buyuktosunoglu, David Albonesi | 2010-11-23 |
| 7739537 | Multiple clock domain microprocessor | David Albonesi, Greg P. Semeraro, Grigorios Magklis, Michael Scott, Sandhya Dwarkadas | 2010-06-15 |
| 7490220 | Multi-cluster processor operating only select number of clusters during each phase based on program statistic monitored at predetermined intervals | Sandhya Dwarkadas, David Albonesi | 2009-02-10 |
| 7478190 | Microarchitectural wire management for performance and power in partitioned architectures | Liqun Cheng, John L. Carter, Naveen Muralimanohar, Karthik Ramani | 2009-01-13 |
| 7089443 | Multiple clock domain microprocessor | David Albonesi, Greg P. Semeraro, Grigorios Magklis, Michael Scott, Sandhya Dwarkadas | 2006-08-08 |
| 6834328 | Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures | Sandhya Dwarkadas, Alper Buyuktosnoglu, David Albonesi | 2004-12-21 |
| 6684298 | Dynamic reconfigurable memory hierarchy | Sandhya Dwarkadas, Alper Buyuktosnoglu, David Albonesi | 2004-01-27 |