Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Daniel Stasiak — 43 Patents

IBM: 39 patents #2,426 of 70,183Top 4%
Qualcomm: 3 patents #4,553 of 12,104Top 40%
Sony: 2 patents #13,023 of 25,231Top 55%
Kabushiki Kaisha Toshiba: 1 patents #13,641 of 21,451Top 65%
Austin, TX: #593 of 18,064 inventorsTop 4%
Texas: #2,236 of 125,132 inventorsTop 2%
Overall (All Time): #69,380 of 4,157,543Top 2%
43 Patents All Time
Daniel Stasiak has been granted 43 US patents while listed as an inventor at IBM. The first was granted in 1990 and the most recent in September 2025. Daniel Stasiak ranks #69,380 of 4,157,543 US inventors in our database (top 1.7%). Patent records list Daniel Stasiak in Austin, TX, US.

Issued Patents All Time

Showing 1–25 of 43 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12431432 Method and apparatus for supplying power to VLSI silicon chips Hassan Naser 2025-09-30
11205620 Method and apparatus for supplying power to VLSI silicon chips Hassan Naser 2021-12-21 $5,237,000
11152378 Reducing error rates with alpha particle protection Hassan Naser, Michael J. Mueller, Kenneth P. Rodbell, Philip J. Oldiges 2021-10-19 $2,168,000
11101211 Semiconductor device with backside inductor using through silicon vias Hassan Naser, Calist Friedman, Matthew A. Cooke 2021-08-24 $4,861,000
10615248 On-die capacitor for a VLSI chip with backside metal plates Hassan Naser 2020-04-07 $1,846,000
10133285 Voltage droop control Sanjay Bhagawan Patil, Martin Saint-Laurent, Rui Li, Bin Liang, Sei Seung Yoon +1 more 2018-11-20 $7,849,000
9851730 Voltage droop control Sanjay Bhagawan Patil, Martin Saint-Laurent, Rui Li, Bin Liang, Sei Seung Yoon +1 more 2017-12-26 $10,564,000
9804650 Supply voltage node coupling using a switch Sanjay Bhagawan Patil, Martin Saint-Laurent 2017-10-31 $7,754,000
8438569 Broadcasting a condition to threads executing on a plurality of on-chip processors Michael Norman Day, Mark Richard Nutter 2013-05-07 $10,737,000
8370780 Method and system for estimating power consumption of integrated circuitry Rajat Chaudhry, Tilman Gloekler, Todd Swanson 2013-02-05 $5,221,000
8020138 Voltage island performance/leakage screen monitor for IP characterization Bruce Balch, Nazmul Habib, Susan K. Lichtensteiger, Richard A. Wachnik 2011-09-13 $4,804,000
7941680 Distributing integrated circuit net power accurately in power and thermal analysis Rajat Chaudhry, Michael Fan Wang 2011-05-10 $6,699,000
7913201 Structure for estimating power consumption of integrated circuitry Rajat Chaudhry, Tilman Gloekler, Todd Swanson 2011-03-22 $5,211,000
7725744 Method and apparatus to generate circuit energy models with multiple clock gating inputs Rajat Chaudhry, James Scott Neely 2010-05-25 $4,007,000
7720667 Method and system for estimating power consumption of integrated circuitry Rajat Chaudhry, Tilman Gloekler, Todd Swanson 2010-05-18 $4,666,000
7656237 Method to gate off PLLS in a deep power saving state without separate clock distribution for power management logic Mack W. Riley, Michael Fan Wang, Stephen Douglas Weitzel 2010-02-02 $8,575,000
7605612 Techniques for reducing power requirements of an integrated circuit Owen Chiang, Christopher McCall Durham, Peter Juergen Klim, Albert J. Van Norstrand, Jr. 2009-10-20 $15,311,000
7535020 Systems and methods for thermal sensing Munehiro Yoshida, Michael Fan Wang, Charles Ray Johns, Hiroki Kihara, Tetsuji Tamura +2 more 2009-05-19
7509606 Method for optimizing power in a very large scale integration (VLSI) design by detecting clock gating opportunities Rajat Chaudhry, Tilman Gloekler, Todd Swanson 2009-03-24 $7,908,000
7503025 Method to generate circuit energy models for macros containing internal clock gating Rajat Chaudhry, James Scott Neely 2009-03-10 $6,331,000
7484187 Clock-gating through data independent logic Cynthia Rae Eisner, Peter Hofstee, Alexander Itskovich 2009-01-27 $4,993,000
7346866 Method and apparatus to generate circuit energy models with clock gating Rajat Chaudhry, James Scott Neely 2008-03-18 $8,037,000
7343499 Method and apparatus to generate circuit energy models with multiple clock gating inputs Rajat Chaudhry, James Scott Neely 2008-03-11 $9,920,000
7284138 Deep power saving by disabling clock distribution without separate clock distribution for power management logic Mack W. Riley, Michael Fan Wang, Stephen Douglas Weitzel 2007-10-16 $5,691,000
7233188 Methods and apparatus for reducing power consumption in a processor using clock signal control Chiaki Takano, Nathan P. Chelstrom, Steven R. Ferguson 2007-06-19 $1,652,000