Issued Patents All Time
Showing 25 most recent of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10608763 | Built-in self-test for receiver channel | John G. Rell, III, Michael W. Harper, Michael B. Spear | 2020-03-31 |
| 9383767 | Circuit design for balanced logic stress | Nathaniel R. Chadwick, Frances S. M. Clougherty, William Paul Hovis, Kirk D. Peterson | 2016-07-05 |
| 9336105 | Evaluation of multiple input signature register results | — | 2016-05-10 |
| 9250645 | Circuit design for balanced logic stress | Nathaniel R. Chadwick, Frances S. M. Clougherty, William Paul Hovis, Kirk D. Peterson | 2016-02-02 |
| 9128150 | On-chip detection of types of operations tested by an LBIST | Michael W. Harper | 2015-09-08 |
| 9057766 | Isolating failing latches using a logic built-in self-test | Ra'ed Mohammad Al-Omari, Michael W. Harper, Cindy Phan | 2015-06-16 |
| 8943458 | Determining chip burn-in workload using emulated application condition | Nathaniel R. Chadwick, Frances S. M. Clougherty, William Paul Hovis, Kirk D. Peterson | 2015-01-27 |
| 8943377 | On-chip detection of types of operations tested by an LBIST | Michael W. Harper | 2015-01-27 |
| 8639855 | Information collection and storage for single core chips to 'N core chips | Michael W. Harper, Larry Scott Leitner | 2014-01-28 |
| 8144689 | Controlling asynchronous clock domains to perform synchronous operations | Nathan P. Chelstrom | 2012-03-27 |
| 8027798 | Digital thermal sensor test implementation without using main core voltage supply | Charles Ray Johns, David Wen-Hao Shan, Michael Fan Wang | 2011-09-27 |
| 7908536 | Testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device | Nathan P. Chelstrom, Steven R. Ferguson | 2011-03-15 |
| 7895426 | Secure power-on reset engine | Ingemar Holm, Ralph C. Koester, Cedric Lichtenau, Thomas Pflueger | 2011-02-22 |
| 7831006 | Circuit to reduce transient current swings during mode transitions of high frequency/high power chips | David William Boerstler, Eskinder Hailu, Michael Fan Wang | 2010-11-09 |
| 7809974 | Circuit to reduce power supply fluctuations in high frequency/high power circuits | David William Boerstler, Eskinder Hailu, Michael Fan Wang | 2010-10-05 |
| 7792154 | Controlling asynchronous clock domains to perform synchronous operations | Nathan P. Chelstrom | 2010-09-07 |
| 7721168 | eFuse programming data alignment verification | — | 2010-05-18 |
| 7711875 | High speed on-chip serial link apparatus | Tilman Gloekler, Ingemar Holm, Ralph C. Koester | 2010-05-04 |
| 7702944 | Dynamic frequency scaling sequence for multi-gigahertz microprocessors | Nathan P. Chelstrom, Michael Fan Wang, Stephen Douglas Weitzel | 2010-04-20 |
| 7698608 | Using a single bank of efuses to successively store testing data from multiple stages of testing | — | 2010-04-13 |
| 7688930 | Using eFuses to store PLL configuration data | Irene Beattie, Nathan P. Chelstrom, Matthew E. Fernsler | 2010-03-30 |
| 7656237 | Method to gate off PLLS in a deep power saving state without separate clock distribution for power management logic | Daniel Stasiak, Michael Fan Wang, Stephen Douglas Weitzel | 2010-02-02 |
| 7627771 | Clock control hierarchy for integrated microprocessors and systems-on-a-chip | Nathan P. Chelstrom, Shoji Sawamura | 2009-12-01 |
| 7620126 | Method and apparatus for detecting frequency lock in a system including a frequency synthesizer | David William Boerstler, Matthew E. Fernsler, Eskinder Hailu, Jieming Qi | 2009-11-17 |
| 7610531 | Modifying a test pattern to control power supply noise | Sang Hoo Dhong, Brian Flachs, Gilles Gervais, Brad W. Michael | 2009-10-27 |