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Self-contained built-in self-test circuit with phase-shifting abilities for high-speed receivers |
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| 10771068 |
Reducing chip latency at a clock boundary by reference clock phase adjustment |
Steven R. Carlough, Susan M. Eickhoff, Michael B. Spear, Gary A. Van Huben |
2020-09-08 |
| 10608763 |
Built-in self-test for receiver channel |
John G. Rell, III, Mack W. Riley, Michael B. Spear |
2020-03-31 |
| 9296246 |
Anti-counterfeiting opto-thermal watermark for electronics |
Ethan E. Cruz, Ryan Michael Kruse, Arden L. Moore, Brian Veraa |
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| 9233572 |
Anti-counterfeiting opto-thermal watermark for electronics |
Ethan E. Cruz, Ryan Michael Kruse, Arden L. Moore, Brian Veraa |
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| 9128150 |
On-chip detection of types of operations tested by an LBIST |
Mack W. Riley |
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| 9057766 |
Isolating failing latches using a logic built-in self-test |
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On-chip detection of types of operations tested by an LBIST |
Mack W. Riley |
2015-01-27 |
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Information collection and storage for single core chips to 'N core chips |
Larry Scott Leitner, Mack W. Riley |
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Electronic fuse apparatus and methodology including addressable virtual electronic fuses |
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